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ES9218PC датащи(PDF) 30 Page - ESS Technology,Inc

номер детали ES9218PC
подробное описание детали  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  101 Pages
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производитель  ESS [ESS Technology,Inc]
домашняя страница  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9218PC датащи(HTML) 30 Page - ESS Technology,Inc

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ES9218P Datasheet
December 6, 2018
CONFIDENTIAL ADVANCE INFORMATION 1.8
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
30
Audio Interface Formats
Several interface formats are provided so that direct connection to common audio processors is possible. The available formats are shown in the following diagrams.
The audio interface format can be set by programming the registers.
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB MSB
31 30
BCLK
LRCLK
LEFT
RIGHT
LEFT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB MSB
31 30
BCLK
LRCLK
LEFT
RIGHT
I2S FORMAT
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
24-bit
MSB
LSB MSB
LSB MSB
23 22
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
SIN
16-bit
MSB
LSB MSB
LSB MSB
15 14
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
24-bit
MSB
LSB MSB
LSB MSB
23 22
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
15 14 13
2
1
0
SIN
16-bit
MSB
LSB MSB
LSB MSB
15 14
Note: for Left-Justified and I2S formats, the following number of BCLKs is present per (left plus right) frame:
• 16-bit mode: 32 BCLKs
• 24-bit mode: 48 BCLKs
• 32-bit mode: 64 BCLKs
Figure 6. Audio Interface Format
DCLK
DSD1, DSD2
DCLK
DSD1, DSD2
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
23 22
MSB
MSB
19 18
MSB
15 14
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 1A
FIGURE 1A
FIGURE 1A
FIGURE 1A
LEFT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
23 22
MSB
MSB
19 18
MSB
15 14
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 1A
FIGURE 1A
FIGURE 1A
FIGURE 1A
LEFT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 2A
FIGURE 2A
FIGURE 2A
FIGURE 2A
RIGHT JUSTIFIED FORMAT
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
31 30 29
2
1
0
23 22 21
2
1
0
23 22 21
2
1
0
SIN
32-bit
MSB
LSB MSB
LSB
MSB
MSB
LSB
LSB
19 18 17
2
1
0
19 18 17
2
1
0
MSB
MSB
LSB
LSB
15 14 13
2
1
0
15 14 13
2
1
0
MSB
MSB
LSB
LSB
23 22
MSB
MSB
19 18
MSB
15 14
MSB
31 30
SIN
24-bit
SIN
20bit
SIN
16bit
BCLK
LRCLK
LEFT
RIGHT
FIGURE 3A
FIGURE 3A
FIGURE 3A
FIGURE 3A
I2S FORMAT
D..
D0
D1
D2
D3
D4
D1
D2
DCLK
FIGURE 4A
D..
D0
D1
D2
D3
D4
D1
D2
DCLK
FIGURE 4B
D..
D0
D1
D2
D3
D4
DSD NORMAL MODE
DSD PHASE MODE



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