CS42L92 datasheet(21/333 Pages) CIRRUS

21 / 333 page

DS1162F2

CS42L92

3 Characteristics and Specifications

Table 3-17. Digital Audio Interface—Slave Mode

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

Parameter 1,2

1.Digital audio interface timing—Slave Mode. Note that BCLK and LRCLK inputs can

be inverted if required; the figure shows the default, noninverted polarity.

2.If AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be within

1% of the applicable SYSCLK_FREQ or ASYNC_CLK_FREQ setting.

Symbol Min Typ Max Units

AIFnBCLK cycle time

tBCY

—

AIFnBCLK pulse width high

BCLK as direct SYSCLK or ASYNCCLK source

All other conditions

tBCH

—

AIFnBCLK pulse width low

BCLK as direct SYSCLK or ASYNCCLK source

All other conditions

tBCL

—

CLOAD = 15 pF (output pins),

BCLK slew (10%–90%) = 3 ns

AIFnLRCLK set-up time to BCLK rising edge

tLRSU

7—

—

AIFnLRCLK hold time from BCLK rising edge

tLRH

0—

—

AIFnTXDAT propagation delay from BCLK falling edge

tDD

0— 12.2

AIFnRXDAT set-up time to BCLK rising edge

tDSU

2—

AIFnRXDAT hold time from BCLK rising edge

tDH

0—

Master LRCLK, AIFnLRCLK propagation delay from BCLK falling edge

tLRD

—— 14.8

CLOAD = 25 pF (output pins),

BCLK slew (10%–90%) = 6 ns

AIFnLRCLK set-up time to BCLK rising edge

tLRSU

7—

AIFnLRCLK hold time from BCLK rising edge

tLRH

0—

AIFnTXDAT propagation delay from BCLK falling edge

tDD

0— 14.2

AIFnRXDAT set-up time to BCLK rising edge

tDSU

2—

AIFnRXDAT hold time from BCLK rising edge

tDH

0—

Master LRCLK, AIFnLRCLK propagation delay from BCLK falling edge

tLRD

—— 15.9

Note: The descriptions above assume noninverted polarity of AIFnBCLK.

Table 3-18. Digital Audio Interface Timing—TDM Mode

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

Parameter 1

1.Digital audio interface timing—

TDM Mode. The timing of the

AIFnTXDAT tristating at the

start and end of the data

transmission is shown.

Min

Typ

Max

Units

Master Mode—CLOAD (AIFnTXDAT) = 15 to

25 pF. BCLK slew (10%–90%) = 3.7ns to 5.6 ns.

AIFnTXDAT enable time from BCLK falling edge

—

AIFnTXDAT disable time from BCLK falling edge

—

Slave Mode—CLOAD (AIFnTXDAT) = 15 pF).

BCLK slew (10%–90%) = 3 ns

AIFnTXDAT enable time from BCLK falling edge

—

AIFnTXDAT disable time from BCLK falling edge

—

12.2

Slave Mode—CLOAD (AIFnTXDAT) = 25 pF).

BCLK slew (10%–90%) = 6 ns

AIFnTXDAT enable time from BCLK falling edge

—

AIFnTXDAT disable time from BCLK falling edge

—

14.2

Note: If TDM operation is used on the AIFnTXDAT pins, it is important that two devices do not attempt to drive the AIFnTXDAT pin

simultaneously. To support this requirement, the AIFnTXDAT pins can be configured to be tristated when not outputting data.

BCLK

(input)

LRCLK

(input)

TXDAT

(output)

RXDAT

(input)

tDSU

tDD

tDH

tLRH

tLRSU

tBCH

tBCL

tBCY

BCLK

TXDAT

AIFnTXDAT enable time

AIFnTXDAT disable time

AIFnTXDAT undriven(tristate)

AIFnTXDAT valid (codec output)

AIFnTXDAT valid

AIFnTXDAT undriven(tristate)

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