CS42L92 datasheet(40/333 Pages) CIRRUS

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DS1162F2

CS42L92

4.2 Input Signal Path

4.2.7

Input Signal Path Digital Volume Control

A digital volume control is provided on each input signal path, providing –64 dB to +31.5 dB gain control in 0.5-dB steps.

An independent mute control is also provided for each input signal path.

Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a

programmable rate. For increasing gain (or unmute), the rate is controlled by IN_VI_RAMP. For decreasing gain (or mute),

the rate is controlled by IN_VD_RAMP.

Note: The IN_VI_RAMP and IN_VD_RAMP fields should not be changed while a volume ramp is in progress.

The IN_VU bits control the loading of the input signal path digital volume and mute controls. When IN_VU is cleared, the

digital volume and mute settings are loaded into the respective control register, but do not change the signal path gain.

The digital volume and mute settings on all of the input signal paths are updated when a 1 is written to IN_VU. This makes

it possible to update the gain of multiple signal paths simultaneously.

Note that, although the digital-volume controls provide 0.5-dB steps, the internal circuits provide signal gain adjustment in

0.125-dB steps. This allows a very high degree of gain control and smooth volume ramping under all operating conditions.

Note: The 0 dBFS level of the IN1–IN4 digital input paths is not equal to the 0 dBFS level of the CS42L92 digital core.

The maximum digital input signal level is –6 dBFS (see Table 3-7). Under 0 dB gain conditions, a –6 dBFS input

signal corresponds to a 0 dBFS input to the CS42L92 digital core functions.

The digital volume control registers are described in Table 4-4 and Table 4-5.

R808 (0x0328)

IN4L_Control

IN4L_HPF

Input Path 4 (Left) HPF Enable

0 = Disabled

1 = Enabled

12:11 IN4_DMIC_

SUP[1:0]

Input Path 4 DMIC Reference Select (sets the DMICDAT4 and DMICCLK4 logic levels)

00 = MICVDD

01 = MICBIAS1

10 = MICBIAS2

11 = Reserved

R810 (0x032A)

DMIC4L_Control

10:8 IN4_

OSR[2:0]

101

Input Path 4 Oversample Rate Control - selects the DMICCLK4 frequency.

010 = 384 kHz

011 = 768 kHz

100 = 1.536 MHz

101 = 3.072 MHz

110 = 6.144 MHz

All other codes are reserved

R812 (0x032C)

IN4R_Control

IN4R_HPF

Input Path 4 (Right) HPF Enable

0 = Disabled

1 = Enabled

Table 4-4. Input Signal Path Digital Volume Control

Bit

Label

Default

Description

R777 (0x0309)

Input_Volume_

Ramp

6:4

IN_VD_RAMP[2:0]

010

Input Volume Decreasing Ramp Rate (seconds/6 dB).

This field should not be changed while a volume ramp is in progress.

000 = 0 ms

001 = 0.5 ms

010 = 1 ms

011 = 2 ms

100 = 4 ms

101 = 8 ms

110 = 15 ms

111 = 30 ms

2:0

IN_VI_RAMP[2:0]

010

Input Volume Increasing Ramp Rate (seconds/6 dB).

This field should not be changed while a volume ramp is in progress.

000 = 0 ms

001 = 0.5 ms

010 = 1 ms

011 = 2 ms

100 = 4 ms

101 = 8 ms

110 = 15 ms

111 = 30 ms

Table 4-3. Input Signal Path Configuration (Cont.)

Bit

Label

Default

Description

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