CS42L92 datasheet(90/333 Pages) CIRRUS

90 / 333 page

DS1162F2

CS42L92

4.3 Digital Core

4.3.16 Isochronous Sample-Rate Converter (ISRC)

The CS42L92 supports multiple signal paths through the digital core. The ISRCs provide sample-rate conversion between

synchronized sample rates on the SYSCLK clock domain, or between synchronized sample rates on the ASYNCCLK clock

domain.

There are two ISRCs on the CS42L92. Each ISRC provides two stereo signal paths between two different sample rates,

as shown in Fig. 4-33.

The sample rates associated with each ISRC can be set independently. Note that the two sample rates associated with

any single ISRC must both be referenced to the same clock domain (SYSCLK or ASYNCCLK).

• When an ISRC is used on the SYSCLK domain, the associated sample rates may be selected from SAMPLE_

RATE_1, SAMPLE_RATE_2, or SAMPLE_RATE_3.

• When an ISRC is used on the ASYNCCLK domain, the associated sample rates are ASYNC_SAMPLE_RATE_1

and ASYNC_SAMPLE_RATE_2.

See Section 4.16 for details of the sample-rate control registers.

Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by ISRCn_FSH, (where

identifies the applicable ISRC 1 or 2). The higher of the two sample rates must be selected by ISRCn_FSH in each case.

R3809 (0x0EE1)

ASRC1_STATUS

ASRC1_IN2L_

ENA_STS

ASRC1 IN2 (left) enable status

(Left channel from ASRC1_RATE2 sample rate to ASRC1_RATE1 sample rate)

0 = Disabled

1 = Enabled

ASRC1_IN2R_

ENA_STS

ASRC1 IN2 (right) enable status

(Right channel from ASRC1_RATE2 sample rate to ASRC1_RATE1 sample rate)

0 = Disabled

1 = Enabled

ASRC1_IN1L_

ENA_STS

ASRC1 IN1 (left) enable status

(Left channel from ASRC1_RATE1 sample rate to ASRC1_RATE2 sample rate)

0 = Disabled

1 = Enabled

ASRC1_IN1R_

ENA_STS

ASRC1 IN1 (right) enable status

(Right channel from ASRC1_RATE1 sample rate to ASRC1_RATE2 sample rate)

0 = Disabled

1 = Enabled

R3810 (0x0EE2)

ASRC1_RATE1

15:11 ASRC1_

RATE1[4:0]

0x00

ASRC1 Sample Rate select for ASRC1 IN1x inputs and ASRC1 IN2x outputs

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x08 = ASYNC_SAMPLE_RATE_1

0x09 = ASYNC_SAMPLE_RATE_2

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All ASRC1_IN1x_SRC fields must be cleared before changing ASRC1_RATE1.

R3811 (0x0EE3)

ASRC1_RATE2

15:11 ASRC1_

RATE2[4:0]

0x08

ASRC1 Sample Rate select for ASRC1 IN2x inputs and ASRC1 IN1x outputs

0x00 = SAMPLE_RATE_1

0x01 = SAMPLE_RATE_2

0x02 = SAMPLE_RATE_3

0x08 = ASYNC_SAMPLE_RATE_1

0x09 = ASYNC_SAMPLE_RATE_2

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All ASRC1_IN1x_SRC fields must be cleared before changing ASRC1_RATE1.

Table 4-27. Digital-Core ASRC Control (Cont.)

Bit

Label

Default

Description

CS42L92 датащи(PDF) 90 Page - Cirrus Logic

CS42L92 датащи(HTML) 90 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL