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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA350B датащи(PDF) 55 Page - STMicroelectronics |
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STA350B датащи(HTML) 55 Page - STMicroelectronics |
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55 / 94 page  DocID018572 Rev 7 55/94 STA350B, STA350BW Register description 94 to power down the power-stage, then the master clock to all internal hardware except the I2C block is gated. This places the IC in a very low power consumption state. 8.6.7 External amplifier power-down The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the FFX4B/EAPD output pin when OCFG = 10. 8.7 Volume control registers (addr 0x06 - 0x0A) 8.7.1 Mute/line output configuration register Line output is active when OCFG = 00 only. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs. 8.7.2 Master volume register 8.7.3 Channel 1 volume Table 50. External amplifier power-down Bit R/W RST Name Description 7 R/W 0 EAPD 0: External power stage power down active 1: Normal operation D7 D6 D5 D4 D3 D2 D1 D0 LOC1 LOC0 Reserved Reserved C3M C2M C1M MMUTE 0000 0000 Table 51. Line output configuration LOC[1:0] Line output configuration 00 Line output fixed - no volume, no EQ 01 Line output variable - CH3 volume effects line output, no EQ 10 Line output variable with EQ - CH3 volume effects line output D7 D6 D5 D4 D3 D2 D1 D0 MV7MV6 MV5MV4 MV3 MV2 MV1MV0 1111 1111 D7 D6 D5 D4 D3 D2 D1 D0 C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 0110 0000 |
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