L99ASC03G datasheet(30/70 Pages) STMICROELECTRONICS

30 / 70 page

Device description

L99ASC03G

30/70

DocID029080 Rev 2

CPOL = 0 and CPHA = 0.

For this mode, input data are sampled on the low-to-high transition of the clock SCK and

output data are changed on the high-to-low transition of SCK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible

output pins and one input pin will be needed to communicate with the device. A fault

condition can be detected by setting CSN to low. If CSN = 0, the SDO pin will reflect the

global error flag (fault condition) of the device.



Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (SDO) will be in high-impedance state. In case CSN is stuck at GND, a

timeout is implemented which sets the SDO back to high-impedance to release the SPI

network. A low signal activates the output driver and a serial communication can be

started. The state during CSN = 0 is called a communication frame.



Serial Data In (SDI)

The input pin is used to transfer data serially into the device. The data applied to the

SDI will be sampled on the rising edge of the SCK signal and shifted into an internal 16-

bit shift register. On the rising edge of the CSN signal, the contents of the shift register

will be transferred to Data Input Register. The writing to the selected Data Input

frame (CSN low). Only frames with 0 or 16 clock pulses are accepted. All others will be

ignored and a communication error will be reported with the next SPI command. This

safety function is implemented to avoid activating of the output stages in case of a

wrong communication frame.

Note:

Due to this safety functionality, SPI daisy chaining is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected IC’s is

recommended.



Serial Data Out (SDO)

The data output driver is activated by a logical low level at the CSN input and will go

from high impedance to a low or high level, depending on the global error flag (fault

condition). The first rising edge of the SCK input after a high-to-low transition of the

CSN pin will transfer the content of the selected status register into the data out shift



Serial Clock (SCK)

The SCK input is used to synchronize the input and output serial bit streams. The data

input (SDI) is sampled on the rising edge of the SCK and the data output (SDO) will

change with the falling edge of the SCK signal. The SPI can be driven with a SCK

frequency up to 4.5 MHz.

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