L9374LF datasheet(65/80 Pages) STMICROELECTRONICS

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L9374LF

Programmers guide

5.2

Status registers

5.2.1

General status (address 0)

Parity-failure:

If a parity-failure occurs during any command write this bit is set. It is cleared by accessing

address 0.

SPI-Clock-failure:

This bit is set by a clock-failure (number of positive edges of SPICLK within SPICS = low is

unequal 16) and is cleared by accessing address 0.

Data-failure:

This bit is set if the master writes invalid data to the configuration-register (Data: SVDT,

CLKIN_S and FSOFF_ALL / CCPWM_Qx / OV_THx, EDGE_SH_OFF). Reset of this bit is

done by accessing address 0. If the master tries to write invalid data to one of the input

registers its content will not be changed (invalid write access is ignored, SPI data failure is

set).

Sync-failure:

This bit is set by a Sync-failure and is cleared when the failure does not exist anymore.

(shows the actual status)

(see Synchronization failure)

MSB

LSB

SGND_L FSON_S

CLKIN_State

CLKIN_F

SYNC_F

DATA_F

SPICLK-F PARITY_F Parity

free

Table 58. Status registers

General status

Number of bits

Bit location

Name

Parity-failure

1 Bit

PARITY_F

SPI-Clock-failure

1 Bit

SPICLK_F

Data-failure

1 Bit

DATA_F

Sync-Failure

1 Bit

SYNC_F

CLKIN-failure

1 Bit

CLKIN_F

EN Status

1 Bit

1MHz / 250kHz Status

2 Bits

D7 - D6

CLKIN_S

Fast Switch On Enable Status

1 Bit

FSON_S

SGND loss

1 Bit

SGND_L

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