6

Functional description

The L3751 device is a native buck controller based on constant frequency voltage mode architecture.

The output voltage VOUT, sensed by the feedback pin (FB), is compared to an internal reference (0.8 V)

providing an error signal on the COMP pin. The comparison between the COMP voltage level and the internal

programmable frequency sawtooth ramp, controls the activation time of the external power switches.

The main internal blocks are shown in the block diagram in Figure 1 and can be summarized as follows:

•

The voltage regulator to supply the internal circuitry and provide a fixed internal reference. This block also

implements a voltage monitor circuitry (UVLO) that checks the input and internal voltages

•

The embedded external N-channel MOSFET drivers and the bootstrap capacitor circuitry to supply the

high-side driver

•

The embedded circuitry that generates the sawtooth ramp to modulate the duty cycle based on the internal

programmable oscillator or the input synchronization signal. The input voltage feedforward is implemented

for improved line transient response

•

The voltage mode error amplifier

•

The PWM comparators and the relative analog and digital circuitry necessary to drive the internal MOSFET

drivers

•

The soft-start circuitry to limit inrush current during the start-up phase and the reference clamper

•

The adjustable senseless or precise valley current limit sensing block and hiccup circuitry to handle overload

and short-circuit conditions

•

The thermal shutdown circuitry to prevent thermal runaway

•

The output voltage monitor circuitry which releases the PGOOD signal if the sensed output voltage is above

87% of the target value.

6.1

Precision enable

The EN/UVLO pin multiplexes the inherent functions as described below:

•

VEN / UVLO < 0.4 typ.: the device is in shutdown mode

•

0.4 V typ. < VEN / UVLO < 1.2 V typ.: device in standby having the VCC regulator active but the device

operation inhibited and SS / TRK pin in low impedance

•

VEN / UVLO > 1.2 V typ.: SS / TRK pin released and the device starts operating. An internal 10 µA current

flows to the external resistor divider to design the enable to UVLO hysteresis.

The central tap of a resistor divider connected to the EN/UVLO pin from VIN designs the enable and undervoltage

lockout thresholds referred to the input voltage as shown in the figure below.

Figure 4. EN / UVLO resistor divider

Rdwn

Rup

+

-

1.2 V

Vin

Enable

Vcc

10 uA

The value of the resistors composing the divider can be calculated as follows:

L3751

Functional description

DS13841 - Rev 1

page 11/41