WM8786

Pre-Production

w

PP Rev 3.0 December 2005

8

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 1 System Clock Timing Requirements

Test Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock cycle time

25

ns

MCLK duty cycle

60:40

40:60

AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

0

10

ns

DOUT propagation delay from BCLK falling edge

0

11

ns