HT49CV7 datasheet(29/48 Pages) HOLTEK

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HT49RV7/HT49CV7

Rev. 1.00

April 20, 2006

VFD Display Control Register

- VFDC

Bit No.

Label

Function

2~0

VGS2~

VGS0

Selects the VFD display mode

000= 4 grids, 16 segments

001= 5 grids, 16 segments

010= 6 grids, 16 segments

011= 7 grids, 15 segments

100= 8 grids, 14 segments

101= 9 grids, 13 segments

110= 10 grids, 12 segments

111= 11 grids, 11 segments

Unused bit, read as

²0²

VFDE

Controls the VFD display

(1=enable; 0=disable)

7~5

VDM2~

VDM0

Sets the VFD dimming quantity

000= set pulse width to 1/16.

001= set pulse width to 2/16.

010= set pulse width to 4/16.

011= set pulse width to 10/16.

100= set pulse width to 11/16.

101= set pulse width to 12/16.

110= set pulse width to 13/16.

111= set pulse width to 14/16.

VFDC (28H) Register

At power-on initial, the 11-grid, 11-segment & 1/16 pulse

width are set and the VFD display is disabled.

VFD clock source may come from the RTC or the sys-

tem clock/4 (fSYS/4), if the fSYS/4 is selected to be the

VFD clock source, when the system is in the HALT

mode, the H/W should automatically turn the VFD off.

Low Voltage Reset

There is a low voltage reset circuit (LVR) implemented in

the microcontroller. This function can be enabled/dis-

abled by options.

The LVR has the same effect or function with the exter-

nal RES signal which performs a chip reset. During

HALT state, the LVR is disabled.

Options

The following shows the configuration options in the HT49RV7/HT49CV7. All these options should be defined in order

to ensure a properly functioning system.

Options

OSC type selection. This option is to determine if an RC or crystal or 32768Hz crystal oscillator is chosen as the sys-

tem clock.

WDT clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC

VFD, RTC and Buzzer clock source selection. There are two types of selections: system clock/4 or RTC OSC

WDT enable/disable selection. WDT can be enabled or disabled by option.

WDT time-out period selection. There are four types of selection: WDT clock source divided by fS/2

12~f

S/2

13,

fS/2

13~f

S/2

14,f

S/2

14~f

S/2

15 or f

S/2

15~f

S/2

CLR WDT times selection. This option defines the method to clear the WDT by instruction.

²One time² means that

the

²CLR WDT² instruction can clear the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2²

instructions have been executed, the WDT can be cleared.

Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: Clock/2~Clock/2

²Clock² means the clock source selected by options.

Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to

wake-up the chip from a HALT by a falling edge. (bit option)

Pull-high selection.

This option is to determine whether the pull-high resistance is viable or not in the input mode of the I/O ports. PA, PB,

PC and PD can be independently selected. (bit option)

RMT Pull-high selection. This option is to determine whether a pull-high resistance is viable or not in the input pin.

I/O pins shared with other function selections.

PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs

PA3/PFD: PA3 can be set as I/O pins or PFD output

VFD driver clock selection. There are seven types of frequency signals for the VFD driver circuits: fS/2

0~f

S/2

²FS² stands for the clock source selection by options.

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