HT49CV7 datasheet(24/48 Pages) HOLTEK

24 / 48 page

HT49RV7/HT49CV7

Rev. 1.00

April 20, 2006

the output signal in output mode of PA0/PA1 will be the

buzzer signal generated by the multi-function timer. The

input mode always remains in its original function. Once

the BZ/BZ option is selected, the buzzer output signal

are controlled by the PA0/PA1 data register only.

The I/O function of PA0/PA1 are shown below.

PA0 I/O

OOOOOOOO

PA1 I/O

OOOOO

PA0 Mode

BBBB

PA1 Mode

C C C

PA0 Data

1 D0 0101

PA1 Data

X D1 D D

PA0 Pad Status

B D0 0B0B

PA1 Pad Status

I D1 DD 0 B

Note:

²I² input; ²O² output

²D, D0, D1² Data

²B² buzzer option, BZ or BZ

²X² don¢t care

²C² CMOS output

The PB port can also be used as A/D converter inputs.

The A/D function will be described later. There is a func-

tion shared with PD0/PD1/PD2/PD3. If the PWM func-

tion is enabled, the PWM0/PWM1/PWM2/PWM3 signal

will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/

PD2/PD3 is operating in the output mode). Writing a

²1²

to PD0~PD3 data register will enable the PWM output

function and writing a

²0² will force the PD0~PD3 to re-

main at

²0². The I/O functions of PD0/PD1/PD2/PD3 are

as shown.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PWM)

O/P

(PWM)

PD0

PD1

PD2

PD3

Logical

Input

Logical

Output

Logical

Input

PWM0

PWM1

PWM2

PWM3

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruc-

tions to avoid consuming power under input floating

state.

PWM

The microcontroller provides a 4 channel and (6+2)/

(7+1) (dependent on options) bits PWM output shared

with PD0/PD1/PD2/PD3. The PWM channels have their

data registers denoted as PWM0 (1AH), PWM1 (1BH),

PWM2 (1CH) and PWM3 (1DH). The frequency source

of the PWM counter comes from fSYS. The PWM regis-

ters are two 8-bit registers. The waveforms of PWM out-

puts are as shown. Once the PD0/PD1/PD2/PD3 are

selected as the PWM outputs and the output function of

PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/

PDC.2/PDC.3=

²0²), writing ²1² to PD0/PD1/PD2/PD3

data register will enable the PWM output function and

writing

²0² will force the PD0/PD1/PD2/PD3 to remain

²0².

A (6+2) bits mode PWM cycle is divided into four modu-

lation cycles (modulation cycle 0~modulation cycle 3).

Each modulation cycle has 64 PWM input clock period.

In a (6+2) bit PWM function, the contents of the PWM

V D D

P F D E N

( P A 3 )

O P 0 ~ O P 7

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P u l l - h i g h

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 / B Z

P A 1 / B Z

P A 2

P A 3 / P F D

P A 4 ~ P A 7

P B 0 / A N 0 ~ P B 7 / A N 7

P C 0 ~ P C 7

P D 0 / P W M 0

P D 1 / P W M 1

P D 2 / P W M 2

P D 3 / P W M 3

P D 4 / I N T 0

P D 5 / I N T 1

P D 6 / T M R 0

P D 7 / T M R 1

I N T 0 f o r P D 4 o n l y

I N T 1 f o r P D 5 o n l y

T M R 0 f o r P D 6 o n l y

T M R 1 f o r P D 7 o n l y

P A 0 / P A 1 / P A 3 / P D 0 / P D 1 / P D 2 / P D 3

B Z / B Z / P F D / P W M 0 / P W M 1 / P W M 2 / P W M 3

C K

Input/Output Ports

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