HT49CV7 datasheet(16/48 Pages) HOLTEK

16 / 48 page

HT49RV7/HT49CV7

Rev. 1.00

April 20, 2006

flags, are located in the status register and are con-

trolled by various microcontroller operations such as the

HALT function or Watchdog Timer. The reset flags are

shown in the table:

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES Wake-up HALT

WDT time-out during normal operation

WDT Wake-up HALT

Note:

²u² stands for unchanged

To ensure that the system oscillator is started and stabi-

lized, the SST (System Start-up Timer) provides an ex-

tra delay of 1024 system clock pulses when the system

awakes from the HALT state or during power-on.

An extra SST delay is added during the power-on pe-

riod, and any wake-up from HALT may enable only the

SST delay.

The functional unit chip reset status is shown below.

Program Counter

000H

Interrupt

Disabled

Prescaler, Divider

Cleared

WDT, RTC, Remote

Control Timer

Cleared. After a master reset,

WDT starts counting

Timer/Event Counter Off

Input/Output Ports

Input mode

Stack Pointer

Points to the top of the stack

R E S

V D D

1 0 0 k W

1 0 k W

0 . 1 m F *

0 . 0 1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

t S S T + t O P D

Reset Timing Chart

W D T

H A L T

W D T

T i m e - o u t

R e s e t

E x t e r n a l

R E S

C o l d

R e s e t

P o w e r - o n D e t e c t i o n

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

W a r m R e s e t

Reset Configuration

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