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HT46C232 датащи(PDF) 22 Page - Holtek Semiconductor Inc |
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HT46C232 датащи(HTML) 22 Page - Holtek Semiconductor Inc |
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22 / 50 page ![]() HT46R232/HT46C232 Rev. 1.40 22 November 23, 2005 Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will au- tomatically reset the device internally. The LVR includes the following specifications: · The low voltage (0.9V~V LVR) has to remain in their original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. · The LVR uses the ²OR² function with the external RES signal to perform chip reset. The relationship between VDD and VLVR is shown below. Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. 5 . 5 V 3 . 0 V 2 . 2 V 0 . 9 V V D D V O P R V L V R 5 . 5 V t A D C A / D c o n v e r s i o n t i m e t A D C A / D c o n v e r s i o n t i m e t A D C A / D c o n v e r s i o n t i m e 0 0 0 B 0 0 0 B 1 0 0 B 0 1 0 B S T A R T E O C B P C R 2 ~ P C R 0 A C S 2 ~ A C S 0 P o w e r - o n R e s e t E n d o f A / D c o n v e r s i o n 1 : D e f i n e P B c o n f i g u r a t i o n 2 : S e l e c t a n a l o g c h a n n e l A / D c l o c k m u s t b e f S Y S / 2 , f S Y S / 8 o r f S Y S / 3 2 t A D C S = 3 2 t A D t A D C = 7 6 t A D N o t e : S t a r t o f A / D c o n v e r s i o n R e s e t A / D c o n v e r t e r A / D s a m p l i n g t i m e t A D C S 1 0 0 B 0 0 0 B S t a r t o f A / D c o n v e r s i o n R e s e t A / D c o n v e r t e r 0 0 0 B 1 . P B p o r t s e t u p a s I / O s 2 . A / D c o n v e r t e r i s p o w e r e d o f f t o r e d u c e p o w e r c o n s u m p t i o n 1 0 1 B 0 0 1 B S t a r t o f A / D c o n v e r s i o n R e s e t A / D c o n v e r t e r d o n ' t c a r e E n d o f A / D c o n v e r s i o n E n d o f A / D c o n v e r s i o n M i n i m u m o n e i n s t r u c t i o n c y c l e n e e d e d , M a x i m u m t e n i n s t r u c t i o n c y c l e s a l l o w e d A / D s a m p l i n g t i m e t A D C S A / D s a m p l i n g t i m e t A D C S A/D Conversion Timing V D D 5 . 5 V V L V R 0 . 9 V 0 V R e s e t S i g n a l R e s e t * 1 * 2 N o r m a l O p e r a t i o n R e s e t L V R D e t e c t V o l t a g e Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. |
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