HT46C232 datasheet(6/50 Pages) HOLTEK

6 / 50 page

HT46R232/HT46C232

Rev. 1.40

November 23, 2005

Functional Description

Execution Flow

The system clock is derived from either a crystal or an

RC oscillator. It is internally divided into four

non-overlapping clocks. One instruction cycle consists

of four system clock cycles. Instruction fetching and ex-

ecution are pipelined in such a way that a fetch takes

one instruction cycle while decoding and execution

takes the next instruction cycle. The pipelining scheme

makes it possible for each instruction to be effectively

executed in a cycle. If an instruction changes the value

of the program counter, two cycles are required to com-

plete the instruction.

Program Counter

- PC

The program counter (PC) is 12 bits wide and it controls

the sequence in which the instructions stored in the pro-

gram ROM are executed. The contents of the PC can

specify a maximum of 4096 addresses. After accessing

a program memory word to fetch an instruction code,

the value of the PC is incremented by 1. The PC then

points to the memory word containing the next instruc-

tion code. When executing a jump instruction, condi-

tional skip execution, loading a PCL register, a

subroutine call, an initial reset, an internal interrupt, an

external interrupt, or returning from a subroutine, the PC

manipulates the program transfer by loading the ad-

dress corresponding to each instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get a proper instruction; oth-

erwise proceed to the next instruction.

The lower byte of the PC (PCL) is a readable and

writeable register (06H). Moving data into the PCL per-

forms a short jump. The destination is within 256 loca-

tions.

When a control transfer takes place, an additional

dummy cycle is required.

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

O S C 2 ( R C o n l y )

P C

Execution Flow

Mode

Program Counter

*11

*10

Initial Reset

000000000000

External Interrupt

000000000100

Timer/Event Counter 0 Overflow

000000001000

Timer/Event Counter 1 Overflow

000000001100

A/D Converter Interrupt

000000010000

2C Bus Interrupt

000000010100

Skip

Program Counter + 2

Loading PCL

*11

*10

Jump, Call Branch

#11

#10

Return from Subroutine

S11

S10

Program Counter

Note:

*11~*0: Program counter bits

S11~S0: Stack register bits

#11~#0: Instruction code bits

@7~@0: PCL bits

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