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HT46C232 датащи(PDF) 15 Page - Holtek Semiconductor Inc |
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HT46C232 датащи(HTML) 15 Page - Holtek Semiconductor Inc |
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15 / 50 page ![]() HT46R232/HT46C232 Rev. 1.40 15 November 23, 2005 To enable the counting operation, the Timer ON bit (T0ON: bit 4 of TMR0C; T10N: bit 4 of TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measure- ment cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Pro- grammable Frequency Divider) output at PA3 by op- tions. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. No matter what the operation mode is, writinga0to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing ²SET [PA].3² instruction to enable PFD output and executing ²CLR [PA].3² instruction to disable PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also re- loads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event coun- ter preload register. The timer/event counter still contin- ues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may re- sults in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly rec- ommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. T 0 M 1 T 0 M 0 T M R 0 T 0 E T 0 M 1 T 0 M 0 T 0 O N P u l s e W i d t h M e a s u r e m e n t M o d e C o n t r o l 8 - s t a g e P r e s c a l e r 8 - 1 M U X f S Y S f I N T T 0 P S C 2 ~ T 0 P S C 0 ( 6 + 2 ) o r ( 7 + 1 ) C o m p a r e P W M T o P D 0 / P D 1 / P D 2 / P D 3 C i r c u i t 1 6 - B i t P r e l o a d R e g i s t e r D a t a B u s R e l o a d O v e r f l o w t o I n t e r r u p t L o w B y t e B u f f e r H i g h B y t e L o w B y t e 1 6 - B i t T i m e r / E v e n t C o u n t e r P F D 0 Timer/Event Counter 0 T 1 M 1 T 1 M 0 T M R 1 T 1 E T 1 M 1 T 1 M 0 T 1 O N P u l s e W i d t h M e a s u r e m e n t M o d e C o n t r o l f S Y S / 4 f I N T 1 6 - B i t P r e l o a d R e g i s t e r D a t a B u s R e l o a d O v e r f l o w t o I n t e r r u p t L o w B y t e B u f f e r H i g h B y t e L o w B y t e 1 6 - B i t T i m e r / E v e n t C o u n t e r P F D 1 Timer/Event Counter 1 M U X 1 / 2 P F D P F D S o u r c e O p t i o n P A 3 D a t a C T R L P F D 0 P F D 1 PFD Source Option |
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