CC2430-RTR1-F32Z datasheet(166/234 Pages) TI

166 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 166 of 232

I-phase

Q-phase

Figure 39: I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 µs

14.2 Command strobes

The CPU uses a set of command strobes

to control operation of the radio in

CC2430.

Command strobes may be viewed as

single byte instructions which each control

some function of the radio. These

command strobes must be used to enable

the frequency synthesizer, enable receive

mode, enable transmit mode and other

functions.

A total of nine command strobes are

defined for the radio and these can be

written individually to the radio or they can

be given in a sequence together with a set

of dedicated software instructions making

up a simple program. All command strobes

from the CPU to the radio pass through

the

CSMA-CA/Command

Strobe

Processor (CSP). Detailed description

about the CSP and how command strobes

are used is given in section 14.34 on page

189.

14.3 RF Registers

The operation of the radio is configured

through a set of RF registers. These RF

registers are mapped to XDATA memory

space as shown in

Figure 13 on page 38.

The RF registers also provide status

information from the radio.

The RF registers control/status bits are

referred to where appropriate in the

following sections while section 14.35 on

page 203 gives a full description of all RF

registers.

14.4 Interrupts

The radio is associated with two interrupt

vectors on the CPU. These are the

RFERR interrupt (interrupt 0) and the RF

interrupt (interrupt 12) with the following

functions

•

RFERR : TXFIFO underflow, RXFIFO

overflow

•

RF : all other RF interrupts given by

RFIF interrupt flags

The RF interrupt vector combines the

interrupts in RFIF shown on page 168.

Note that these RF interrupts are rising-

edge triggered. Thus an interrupt is

generated when e.g. the SFD status flag

goes from 0 to 1.

The RF interrupt can also be used to

trigger a timer capture in Timer 1.

The RFIF interrupt flags are described in

the next section.

14.4.1 Interrupt registers

Two of the main interrupt control SFR

registers are used to enable the RF and

RFERR

interrupts.

These

are

the

following:

•

RFERR

: IEN0.RFERRIE

•

: IEN2.RFIE

Two main interrupt flag SFR registers hold

the RF and RFERR interrupt flags. These

are the following:

•

RFERR

: TCON.RFERR

•

: S1CON.RFIF

Refer to section 12.7 on page 52 for

details about the interrupts.

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