CC2430-RTR1-F32Z datasheet(100/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 100 of 232

0000h

T1CC0

OVFL

Figure 22 : Up/down mode

13.3.6 Channel Mode Control

The channel mode is set with each channel’s

control and status register T1CCTLn. The

settings include input capture and output

compare modes.

13.3.7 Input Capture Mode

When a channel is configured as an input

capture channel, the I/O pin associated with

that channel, is configured as an input. After

the timer has been started, a rising edge,

falling edge or any edge on the input pin will

trigger a capture of the 16-bit counter contents

into the associated capture register. Thus the

timer is able to capture the time when an

external event takes place.

Note: before an I/O pin can be used by the

timer, the required I/O pin must be configured

as a Timer 1 peripheral pin as described in

section 13.1.3 on page 70 .

The channel input pin is synchronized to the

internal system clock. Thus pulses on the input

pin must have a minimum duration greater

than the system clock period.

The contents of the 16-bit capture register is

read out from registers T1CCnH:T1CCnL.

When the capture takes place the interrupt flag

for

the

channel

set.

This

bit

T1CTL.CH0IF for channel 0, T1CTL.CH1IF

for channel 1, and T1CTL.CH2IF for channel

2. An interrupt request is generated if the

corresponding

interrupt

mask

bit

T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM,

respectively, is set.

13.3.8 RF Event Capture

Each timer channel may be configured so that

an RF interrupt event will trigger a capture

instead of the normal input pin capture. This

function is selected with the register bit

T1CCTLx.CPSEL, which selects to use either

the input pin or the RF interrupt as capture

event. When RF is selected as capture input,

the interrupt source(s) enabled by RFIM (see

section 14.4.1 on page 166) will trigger a

capture. In this way the timer can be used to

capture a value when e.g. a start of frame

delimiter (SFD) is detected.

13.3.9 Output Compare Mode

In output compare mode the I/O pin associated

with a channel is set as an output. After the

timer has been started, the contents of the

counter is compared with the contents of the

channel compare register T1CCnH:T1CCnL. If

the compare register equals the counter

contents, the output pin is set, reset or toggled

according to the compare output mode setting

of T1CCTLn.CMP. Note that all edges on

output pins are glitch-free when operating in a

given output compare mode. Writing to the

compare register T1CCnL is buffered so that a

value written to T1CCnL does not take effect

until the corresponding high order register,

T1CCnH is written. For output compare modes

1-3, a new value written to the compare

registers have been written. For other output

compare modes the new value written to the

compare register take effect when the timer

reaches 0x0000.

Note that channel 0 has fewer output compare

modes because T1CC0H:T1CC0L has a

special function in modes 6 and 7, meaning

these modes would not be useful for channel

When a compare occurs, the interrupt flag for

the channel is set. This bit is T1CTL.CH0IF

for channel 0, T1CTL.CH1IF for channel 1,

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