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CC2430-RTR1-F32Z датащи(PDF) 164 Page - Texas Instruments

номер детали CC2430-RTR1-F32Z
подробное описание детали  A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM
PDF  234 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

CC2430-RTR1-F32Z датащи(HTML) 164 Page - Texas Instruments

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CC2430
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 164 of 232
14 Radio
LNA
DIGITAL
DEMODULATOR
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
- Frame
synchronization
DIGITAL
MODULATOR
- Data spreading
- Modulation
Σ
AUTOMATIC GAIN CONTROL
TX POWER CONTROL
TX/RX CONTROL
ADC
ADC
DAC
DAC
0
90
FREQ
SYNTH
Power
Control
PA
FFCTRL
Register bus
CSMA/CA
STROBE
PROCESSOR
RADIO
REGISTER
BANK
IRQ
HANDLING
SFR bus
Figure 37: CC2430 Radio Module
A simplified block diagram of the IEEE
802.15.4 compliant radio inside
CC2430 is
shown in Figure 37. The radio core is
based on the industry leading
CC2420 RF
transceiver.
CC2430 features a low-IF receiver. The
received RF signal is amplified by the low-
noise amplifier (LNA) and down-converted
in quadrature (I and Q) to the intermediate
frequency (IF). At IF (2 MHz), the complex
I/Q signal is filtered and amplified, and
then digitized by the ADCs.
Automatic
gain control, final channel filtering, de-
spreading, symbol correlation and byte
synchronization are performed digitally.
An interrupt indicates that a start of frame
delimiter has been detected.
CC2430
buffers the received data in a 128 byte
receive FIFO. The user may read the FIFO
through
an
SFR
interface.
It
is
recommended to use direct memory
access (DMA) to move data between
memory and the FIFO.
CRC is verified in hardware. RSSI and
correlation values are appended to the
frame. Clear channel assessment, CCA, is
available through an interrupt in receive
mode.
The
CC2430 transmitter is based on direct
up-conversion. The data is buffered in a
128 byte transmit FIFO (separate from the
receive FIFO). The preamble and start of
frame delimiter are generated in hardware.
Each symbol (4 bits) is spread using the
IEEE 802.15.4 spreading sequence to 32
chips and output to the digital-to-analog
converters (DACs).
An analog low pass filter passes the signal
to the quadrature (I and Q) up-conversion
mixers. The RF signal is amplified in the
power amplifier (PA) and fed to the
antenna.
The internal T/R switch circuitry makes the
antenna interface and matching easy. The
RF connection is differential. A balun may
be used for single-ended antennas. The
biasing of the PA and LNA is done by
connecting TXRX_SWITCH to RF_P and
RF_N through an external DC path.
The frequency synthesizer includes a
completely on-chip LC VCO and a 90
degrees phase splitter for generating the I
and Q LO signals to the down-conversion
mixers in receive mode and up-conversion
mixers in transmit mode. The VCO
operates in the frequency range 4800 –



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