CC2430-RTR1-F64Z datasheet(219/234 Pages) TI

219 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 219 of 232

Bit

Name

Reset

R/W

Description

Reserved, read as 0.

6:0

FIFOP_THR[6:0]

0x40

R/W

Sets the number of bytes in RXFIFO that is required for

FIFOP to go high.

Table 93: Register IOCFG0 (0xDF4F)

Bit

Name

Reset

R/W

Description

Reserved, read as 0.

OE_CCA

R/W

CCA is output on P1.7 when this bit is 1

IO_CCA_POL

R/W

Polarity of the IO_CCA signal. This bit is xor’ed with the

internal CCA signal.

4:0

IO_CCA_SEL

000000

R/W

Multiplexer setting for the CCA signal. Must be 0x00 in

order to output the CCA status.

Table 94: Register IOCFG1 (0xDF50)

Bit

Name

Reset

R/W

Description

Reserved, read as 0.

OE_SFD

R/W

SFD is output on P1.6 when this bit is 1

IO_SFD_POL

R/W

Polarity of the IO_SFD signal. This bit is xor’ed with the

internal SFD signal.

4:0

IO_SFD_SEL

000000

R/W

Multiplexer setting for the SFD signal. Must be 0x00 in order

to output the SFD status

Table 95: Register IOCFG2 (0xDF51)

Bit

Name

Reset

R/W

Description

7:6

Reserved, read as 0.

5:4

HSSD_SRC

R/W

Configures the HSSD interface. Only the first 4 settings

(compared to CC2420) are used.

00 : Off

01 : Output AGC status (gain setting/peak detector

status/accumulator value)

10 : Output ADC I and Q values

11 : Output I/Q after digital down mix and channel filtering

OE_FIFOP

R/W

FIFOP is output on P1.5 when this bit is 1.

IO_FIFOP_POL

R/W

Polarity of the IO_FIFOP signal. This bit is xor’ed with the

internal FIFOP signal

OE_FIFO

R/W

FIFO is output on P1.4 when this bit is 1

IO_FIFO_POL

R/W

Polarity of the IO_FIFO signal. This bit is xor’ed with the

internal FIFO signal

Table 96: Register IOCFG3 (0xDF52)

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