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CC2430-RTR1-F64Z датащи(PDF) 216 Page - Texas Instruments

номер детали CC2430-RTR1-F64Z
подробное описание детали  A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM
PDF  234 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

CC2430-RTR1-F64Z датащи(HTML) 216 Page - Texas Instruments

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CC2430
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 216 of 232
Bit
Name
Reset
R/W
Description
7:4
-
0
R0
Reserved, read as 0.
3:2
LNAMIX_GAINMODE_O
[1:0]
00
R/W
LNA / Mixer Gain mode override setting
00 : Gain mode is set by AGC algorithm
01 : Gain mode is always low-gain
10 : Gain mode is always med-gain
11 : Gain mode is always high-gain
1:0
LNAMIX_GAINMODE[1:0]
00
R
Status bit, defining the currently selected gain mode
selected by the AGC or overridden by the
LNAMIX_GAINMODE_O setting.
Table 75: Register AGCCTRLL (0xDF27)
Bit
Name
Reset
R/W
Description
7:6
-
0
R0
Reserved, read as 0.
5:0
FSM_FFCTRL_STATE[5:0
]
-
R
Gives the current state of the FIFO and Frame Control
(FFCTRL) finite state machine.
Table 76: Register FSMSTATE (0xDF39)
Bit
Name
Reset
R/W
Function
7
ADC_CLOCK_DISABLE
0
R/W
ADC Clock Disable
0 : Clock enabled when ADC enabled
1 : Clock disabled, even if ADC is enabled
6:0
ADC_I[6:0]
-
R
Returns the current ADC I-branch value.
Table 77: Register ADCTSTH (0xDF3A)
Bit
Name
Reset
R/W
Function
7:6
-
0
R0
Reserved, read as 0.
6:0
ADC_Q[6:0]
-
R
Returns the current ADC Q-branch value.
Table 78: Register ADCTSTL (0xDF3B)



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