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CC2430-RTR1-F64Z датащи(PDF) 173 Page - Texas Instruments |
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CC2430-RTR1-F64Z датащи(HTML) 173 Page - Texas Instruments |
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173 / 234 page ![]() CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 173 of 232 significant degradation of the receiver performance. Soft decision is used at the chip level, i.e. the demodulator does not make a decision for each chip, only for each received symbol. De-spreading is performed using over-sampling symbol correlators. Symbol synchronization is achieved by a continuous start of frame delimiter (SFD) search. When an SFD is detected, data is written to the RXFIFO and may be read out by the CPU at a lower bit rate than the 250 kbps generated by the receiver. The CC2430 demodulator also handles symbol rate errors in excess of 120 ppm without performance degradation. Resynchronization is performed continuously to adjust for error in the incoming symbol rate. The RF register MDMCTRL1H.CORR_THR control bits should be written to 20 to set the threshold for detecting IEEE 802.15.4 start of frame delimiters. Digital IF Channel Filtering ADC Digital Data Filtering Frequency Offset Compensation Symbol Correlators and Synchronisation RSSI Generator I / Q Analog IF signal Data Symbol Output RSSI Average Correlation Value (may be used for LQI) Figure 44: Demodulator Simplified Block Diagram 14.12 Frame Format CC2430 has hardware support for parts of the IEEE 802.15.4 frame format. This section gives a brief summary to the IEEE 802.15.4 frame format, and describes how CC2430 is set up to comply with this. Figure 45 [1] shows a schematic view of the IEEE 802.15.4 frame format. Similar figures describing specific frame formats (data frames, beacon frames, acknowledgment frames and MAC command frames) are included in [1]. Figure 45: Schematic view of the IEEE 802.15.4 Frame Format [1] 14.13 Synchronization header The synchronization header (SHR) consists of the preamble sequence followed by the start of frame delimiter (SFD). In [1], the preamble sequence is defined to be four bytes of 0x00. The SFD is one byte, set to 0xA7. In CC2430, the preamble length and SFD is configurable. The default values are PHY Layer Frame Control Field (FCF) Data Sequence Number 2 1 Bytes: Address Information 0 to 20 Frame payload n Frame Check Sequence (FCS) 2 MAC Header (MHR) MAC Payload MAC Footer (MFR) Frame Length MAC Protocol Data Unit (MPDU) Start of frame Delimiter (SFD) Bytes: 1 1 5 + (0 to 20) + n Preamble Sequence 4 Synchronisation Header (SHR) PHY Header (PHR) PHY Service Data Unit (PSDU) PHY Protocol Data Unit (PPDU) 11 + (0 to 20) + n MAC Layer |
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