CC2430-RTR1-F64Z datasheet(172/234 Pages) TI

172 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 172 of 232

Figure 43.

The RFIF.IRQ_SFD interrupt flag goes

high and the RF interrupt is requested

when the SFD field has been completely

transmitted. It goes low again when the

complete MPDU (as defined by the length

field) has been transmitted or if an

underflow is detected. The interrupt

RFERR is asserted when enabled. See

section 14.17.1 on page 176 for more

information on TXFIFO underflow.

As can be seen from comparing Figure 41

and

Figure

43,

the

RFSTATUS.SFD

bit

behaves very similarly during reception

and transmission of a data frame. If the

RFSTATUS.SFD bits of the transmitter and

the receiver are compared during the

transmission of a data frame, a small

delay of approximately 2 µs can be seen

because of bandwidth limitations in both

the transmitter and the receiver.

Preamble

SFD

Lengt

Data

transmitted

over RF

SFD

tra

itte

tra

itte

rfl

MAC Protocol Data Unit (MPDU)

str

12 symbol periods

Automatically generated

preamble and SFD

Data fetched

from TXFIFO

CRC

generated

Figure 43: SFD status activity example during transmit

14.10 General control and status

In receive mode, the RFIF.IRQ_FIFOP

interrupt flag and RF interrupt request can

be used to interrupt the CPU when a

threshold has been exceeded or a

complete frame has been received.

In receive mode, the RFSTATUS.FIFO bit

can be used to detect if there is data at all

in the receive FIFO.

The RFIF.IRQ_SFD interrupt flag can be

used to extract the timing information of

transmitted and received data frames. The

RFIF.IRQ_SFD bit will go high when a

start

frame

delimiter

has

been

completely detected / transmitted.

For

debug

purposes,

the

RFSTATUS.SFD,

RFSTATUS.FIFO,

RFSTATUS.FIFOP and RFSTATUS.CCA

bits can be output onto P1.7 – P1.4 I/O

pins to monitor the status of these signals

as selected by the IOCFG0, IOCFG1

and IOCFG2 register.

The polarity of these signals given on the

debug outputs can also be controlled by

the IOCFG0-2 registers, if needed.

14.11 Demodulator, Symbol

Synchronizer and Data Decision

The block diagram for the

CC2430

demodulator is shown in Figure 44.

Channel filtering and frequency offset

compensation is performed digitally. The

signal level in the channel is estimated to

generate the RSSI level (see the RSSI /

Energy Detection section on page 181 for

more information). Data filtering is also

included for enhanced performance.

With the ±40 ppm frequency accuracy

requirement from [1], a compliant receiver

must be able to compensate for up to 80

ppm or 200 kHz. The

CC2430 demodulator

tolerates up to 300 kHz offset without

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