CC2430-RTR1-F64Z datasheet(170/234 Pages) TI

170 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 170 of 232

RFD (0xD9) – RF Data

Bit

Name

Reset

R/W

Description

7:0

RFD[7:0]

0x00

R/W

Data written to the register is written to the

TXFIFO. When reading this register, data from the

RXFIFO is read

14.6 DMA

It is possible, and in most cases

recommended, to use direct memory

access (DMA) to move data between

memory and the radio. The DMA controller

is described in section 13.2. Refer to this

section for a detailed description on how to

setup and use DMA transfers.

To support the DMA controller there is one

DMA trigger associated with the radio, this

is the RADIO DMA trigger (DMA trigger

19). The RADIO DMA trigger is activated

by two events. The first event to cause a

RADIO DMA trigger, is when the first data

is present in the RXFIFO, i.e. when the

RXFIFO goes from the empty state to the

non-empty state. The second event that

causes a RADIO DMA trigger, is when

data is read from the RXFIFO (through

RFD SFR register) and there is still more

data available in the RXFIFO.

14.7 Receive mode

In receive mode, the interrupt flag

RFIF.IRQ_SFD goes high and the RF

interrupt is requested after the start of

frame delimiter (SFD) field has been

completely received. If address recognition

disabled

successful,

the

RFSTATUS.SFD bit goes low again only

after the last byte of the MPDU has been

received. If the received frame fails

address recognition, the RFSTATUS.SFD

bit goes low immediately. This is illustrated

in Figure 41.

The RFSTATUS.FIFO bit is high when

there is one or more data bytes in the

RXFIFO. The first byte to be stored in the

RXFIFO is the length field of the received

frame, i.e. the RFSTATUS.FIFO bit is set

high when the length field is written to the

RXFIFO. The RFSTATUS.FIFO bit then

remains high until the RXFIFO is empty.

The RF register RXFIFOCNT contains the

number of bytes present in the RXFIFO.

The RFSTATUS.FIFOP bit is high when

the number of unread bytes in the RXFIFO

exceeds the threshold programmed into

IOCFG0.FIFOP_THR.

When

address

recognition

enabled

the

RFSTATUS.FIFOP bit will not go high until

the incoming frame passes address

recognition, even if the number of bytes in

the RXFIFO exceeds the programmed

threshold.

The RFSTATUS.FIFOP bit will also go

high when the last byte of a new packet is

received, even if the threshold is not

exceeded. If so the RFSTATUS.FIFOP bit

will go back to low once one byte has

been read out of the RXFIFO.

When address recognition is enabled, data

should not be read out of the RXFIFO

before the address is completely received,

since the frame may be automatically

flushed by

CC2430 if it fails address

recognition. This may be handled by using

the RFSTATUS.FIFOP bit, since this bit

does not go high until the frame passes

address recognition.

Figure 42 shows an example of status bit

activity when reading a packet from the

RXFIFO. In this example, the packet size

is 8 bytes, IOCFG0.FIFOP_THR = 3 and

MODEMCTRL0.AUTOCRC is set. The length

will be 8 bytes, RSSI will contain the

average RSSI level during receiving of the

packet and FCS/corr contain information

of FCS check result and the correlation

levels.

14.8 RXFIFO overflow

The RXFIFO can only contain a maximum

of 128 bytes at a given time. This may be

divided between multiple frames, as long

as the total number of bytes is 128 or less.

If an overflow occurs in the RXFIFO, this is

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