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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CC2430-RTR1-F64 датащи(PDF) 130 Page - Texas Instruments |
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CC2430-RTR1-F64 датащи(HTML) 130 Page - Texas Instruments |
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130 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 130 of 232 ADCH (0xBB) – ADC Data High Bit Name Reset R/W Description 7:0 ADC[13:6] 0x00 R Most significant part of ADC conversion result. ADCCON1 (0xB4) – ADC Control 1 Bit Name Reset R/W Description 7 EOC 0 R H0 End of conversion Cleared when both ADCH and ADCL has been read. If a new conversion is completed before the previous data has been read, the EOC bit will remain high. 0 conversion not complete 1 conversion completed 6 ST 0 R/W1 Start conversion. Read as 1 until conversion has completed 0 no conversion in progress 1 start a conversion sequence if ADCCON1.STSEL = “11” and no sequence is running. 5:4 STSEL[1:0] 11 R/W Start select. Selects which event that will start a new conversion sequence. 00 External trigger on P2_0 pin. 01 Full speed. Do not wait for triggers. 10 Timer 1 channel 0 compare event 11 ADCCON1.ST = 1 3:2 RCTRL[1:0] 00 R/W Controls the 16 bit random number generator. When written 01, the setting will automatically return to 00 when operation has completed. 00 Normal operation. (13x unrolling) 01 Clock the LFSR once (no unrolling). 10 Reserved 11 Stopped. Random number generator is turned off. 1:0 - 11 R/W Reserved. Always set to 11. |
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