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CC2430-RTR1-F64 датащи(PDF) 128 Page - Texas Instruments |
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CC2430-RTR1-F64 датащи(HTML) 128 Page - Texas Instruments |
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128 / 234 page ![]() CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 128 of 232 the differential inputs consist of the input pairs AIN0-1, AIN2-3, AIN4-5 and AIN6-7. In addition to the input pins AIN0-AIN7, the output of an on-chip temperature sensor can be selected as an input to the ADC for temperature measurements. It is also possible to select a voltage corresponding to AVDD_SOC/3 as an ADC input. This input allows the implementation of e.g. a battery monitor in applications where this feature is required. 13.7.2.3 ADC conversion sequences The ADC will perform a sequence of conversions, and move the results to memory (through DMA) without any interaction from the CPU. The ADCCON2.SCH register bits are used to define an ADC conversion sequence, from the ADC inputs. A conversion sequence will contain a conversion from each channel from 0 up to and including the channel number programmed in ADCCON2.SCH when ADCCON2.SCH is set to a value less than 8. The single-ended inputs AIN0 to AIN7 are represented by channel numbers 0 to 7 in ADCCON2.SCH. Channel numbers 8 to 11 represent the differential inputs consisting of AIN0-AIN1, AIN2-AIN3, AIN4-AIN5 and AIN6-AIN7. Channel numbers 12 to 15 represent GND, internal voltage reference, temperature sensor and AVDD_SOC/3, respectively. When ADCCON2.SCH is set to a value between 8 and 12, the sequence will start at channel 8. For even higher settings, only single conversions are performed. In addition to this sequence of conversions, the ADC can be programmed to perform a single conversion from any channel as soon as the sequence has completed. This is called an extra conversion and is controlled with the ADCCON3 register. The conversion sequence can also be influenced with the ADCCFG register (see section 13.1.5 on page 72). The eight analog inputs to the ADC comes from IO pins, which are not necessarily programmed to be analog inputs. If a channel should normally be part of a sequence, but the corresponding analog input is disabled in the ADCCFG, then that channel will be skipped. For channels 8 to 12, both input pins must be enabled. 13.7.2.4 ADC Operating Modes This section describes the operating modes and initialization of conversions. The ADC has three control registers: ADCCON1, ADCCON2 and ADCCON3. These registers are used to configure the ADC and to report status. The ADCCON1.EOC bit is a status bit that is set high when a conversion ends and cleared when ADCH is read. The ADCCON1.ST bit is used to start a sequence of conversions. A sequence will start when this bit is set high, ADCCON1.STSEL=”11” and no conversion is currently running. When the sequence is completed, this bit is automatically cleared. The ADCCON1.STSEL bits select which event that will start a new sequence of conversions. The options which can be selected are rising edge on external pin P2_0, end of previous sequence, a Timer 1 channel 0 compare event or ADCCON1.ST=’1’. The ADCCON2 register controls how the sequence of conversions is performed. ADCCON2.SREF is used to select the reference voltage. The reference voltage should only be changed when no conversion is running. The ADCCON2.SDIV bits select the decimation rate (and thereby also the resolution and time required to complete a conversion and sample rate). The decimation rate should only be changed when no conversion is running. The last channel of a sequence is selected with the ADCCON2.SCH bits. The ADCCON3 register controls the channel number, reference voltage and decimation rate for the extra conversion. The extra conversion will take place immediately after the ADCCON3 register is updated. The coding of the register bits is exactly as for ADCCON2. |
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