8.5

TDM_CTRL_REG (2Eh)

(R/W)

TDM_pd

Delayed

data_valid

mapping

0(1)

WCLK_fq1

WCLK_fq0

0(1)

1. This bit must be set to 0 for the correct operation of the device.

TDM_pd

Enables TDM. Default value: 1

(0: TDM on; 1: TDM off)

Delayed

TDM delayed configuration. Default value: 1

(0: TDM no delayed configuration; 1: TDM delayed configuration)

data_valid

TDM data valid. Default value: 1

(0: data valid on the rise edge of BCLK; 1: data valid on the falling edge of BCLK)

mapping

TDM mapping. Default value: 1

(0: AXEX → SLOT0; AXEY → SLOT1; AXEZ → SLOT2;

1: AXEX → SLOT4; AXEY → SLOT5; AXEZ → SLOT6)

WCLK_fq [1:0]

TDM clock frequencies. Default value: 00

(00: WCLK = 8 kHz;

01: WCLK = 16 kHz;

10: WCLK = 24 kHz)

8.6

CTRL_REG_2 (2Fh)

(R/W)

1(1)

1(1)

1(1)

0(2)

0(2)

0(2)

0(2)

ODR_AUTO_

EN

1. This bit must be set to 1 for the correct operation of the device.

2. This bit must be set to 0 for the correct operation of the device.

ODR_AUTO_EN

Enables auto ODR. Default value: 1

(0: auto ODR and BCLK disabled(1); 1: auto ODR and BCLK enabled(2))

1. In this case it is mandatory to set TDM_CTRL_REG (2Eh) bits 2 and 1 to match the WCLK sampling rate and TDM_cmax

(24h-25h) to match the BCLK/WCLK ratio

2. AIS25BA automatically measures the ratio r = MCLK/WCLK. The WCLK frequency is internally determined as FW=12.288

MHz/r. FW is used to configure automatically the decimation ratio between the ADC and TDM input data rate (same as

TDM output data rate) bypassing TDM_CTRL_REG (2Eh) bits 2 and 1 configuration. When ODR_AUTO is 1 also the

BCLK/WCLK ratio is automatically computed for proper TDM configuration as described in TDM_cmax (24h-25h).

AIS25BA

TDM_CTRL_REG (2Eh)

DS14019 - Rev 1

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