4.5

TDM configurations

All the AIS25BA TDM configurations programmable over the I²C interface are explained in detail in the following

subsections.

4.5.1

Configuration 1

•

No delay: SLOT0 data MSB is sampled on the first rising edge of BCLK after rising edge of WCLK (delayed

I²C register TDM_CTRL_REG (2Eh) bit 6 equal to zero)

•

Data valid: data valid on the rising edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal

to zero)

delay

Note:

Setup and hold times are defined in Table 5. TDM interface characteristics.

4.5.2

Configuration 2

•

No delay: SLOT0 data MSB is sampled on the first falling edge of BCLK after rising edge of WCLK (delayed

I²C register TDM_CTRL_REG (2Eh) bit 6 equal to zero)

•

Data valid: data valid on the falling edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5

equal to one)

delay

Note:

Setup and hold times are defined in Table 5. TDM interface characteristics.

AIS25BA

TDM configurations

DS14019 - Rev 1

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