5.2

I²C interface details

The transaction on the bus is started through a start signal. A start condition is defined as a high to low transition

on the data line while the SCL line is held high (refer to the ST condition in the following paragraph). After this

signal has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after

the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master

is receiving data from the slave or transmitting data to the slave (SAD subsequences). When an address is sent,

each device in the system compares the first seven bits after a start condition with its address. If they match, the

device considers itself addressed by the master. The address can be made up of a programmable part and a

fixed part, thus allowing more than one device of the same type to be connected to the I²C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge

pulse. The receiver must then pull the data line low so that it remains stable low during the high period

of the acknowledge clock pulse (SAK subsequence). A receiver that has been addressed must generate an

acknowledge after each byte of data has been received. The I²C embedded inside the AIS25BA behaves like

a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is

sent, once a slave acknowledge has been returned (SAK), an 8-bit subaddress is transmitted (SUB): the 7 LSB

represent the actual register address while the MSB enables address auto-increment. If the MSB of the SUB

field is 1, the SUB (register address) is automatically incremented to allow multiple data read/write at increasing

addresses. Otherwise, if the MSB of the SUB field is 0, the SUB remains unchanged and multiple read/write on

the same address can be performed. If the LSB of the slave address is 1 (read), a repeated start (SR) condition

must be issued after the subaddress byte; if the LSB is 0 (write) the master transmits to the slave with direction

unchanged.

5.3

I²C slave address

The slave address is equal to 001100yx (TDM mode, where y = not(I2C_A0 pin)) or in case of writing or reading

respectively.

5.4

I²C read and write sequences

Previous subsequences are used for the actual write and read sequences described in the tables below.

Master

ST

SAD + W

SUB

DATA

SP

Slave

SAK

SAK

SAK

Master

ST

SAD + W

SUB

DATA

DATA

SP

Slave

SAK

SAK

SAK

SAK

Master

ST

SAD + W

SUB

SR

SAD + R

NMAK

SP

Slave

SAK

SAK

SAK

DATA

Master

ST

SAD+W

SUB

SR

SAD+R

MAK

MAK

NMAK

SP

Slave

SAK

SAK

SAK

DATA

DATA

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred

per transfer is unlimited. Data is transferred with the most significant bit (MSB) first. If a slave receiver doesn’t

acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function)

the data line must be left high by the slave. The master can then abort the transfer. A low to high transition on the

SDA line while the SCL line is high is defined as a stop condition (SP). Each data transfer must be terminated by

the generation of a stop condition.

AIS25BA

I²C interface details

DS14019 - Rev 1

page 15/31