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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LMK6C датащи(PDF) 10 Page - Texas Instruments |
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LMK6C датащи(HTML) 10 Page - Texas Instruments |
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10 / 45 page  Over Recommended Operating Conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT JPCIe1- SRNS PCIe Gen 1 SRNS jitter Fout = 100 MHz TBD ps JPCIe2-cc PCIe Gen 2 Common Clock jitter (jitter limit = 3 ps) Fout = 100 MHz TBD ps JPCIe2- SRNS PCIe Gen 2 SRNS jitter Fout = 100 MHz TBD ps JPCIe3-cc PCIe Gen 3 Common Clock jitter (jitter limit = 1 ps) Fout = 100 MHz TBD ps JPCIe3- SRNS PCIe Gen 3 SRNS jitter Fout = 100 MHz TBD ps JPCIe4-cc PCIe Gen 4 Common Clock jitter (jitter limit = 500 fs) Fout = 100 MHz 140 TBD fs JPCIe4- SRNS PCIe Gen 4 SRNS jitter Fout = 100 MHz TBD fs JPCIe5-cc PCIe Gen 5 Common Clock jitter (jitter limit = 150 fs) Fout = 100 MHz 45 TBD fs JPCIe5- SRNS PCIe Gen 5 SRNS jitter Fout = 100 MHz TBD fs JPCIe6-cc PCIe Gen 6 Common Clock jitter (jitter limit = 100 fs) Fout = 100 MHz TBD fs JPCIe6- SRNS PCIe Gen 6 SRNS jitter Fout = 100 MHz TBD fs LVCMOS - Clock Output Jitter RJ Random Phase Jitter Fout = 24 MHz, Integration BW: 12 kHz - 5 MHz 200 fs RJ Random Phase Jitter Fout = 156.25 MHz, Integration BW: 12 kHz - 20 MHz 200 500 fs RJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 0.7 ps RJITT,PK Peak-peak Period Jitter Fout ≥ 25 MHz 7 ps (1) Excluding Load current (2) DC Load condition 7.8 Timing Diagrams VOD = VOH - VOL OUTx_N OUTx_P VOUT-DIFF = 2 × VOD 0 V 20% 80% tR tF VOH VOL Figure 7-1. Differential Output Voltage and Rise/Fall Time LMK6C SNAS826A – APRIL 2022 – REVISED JULY 2022 www.ti.com 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LMK6C |
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