VSC8540RT datasheet(60/87 Pages) MICROCHIP

60 / 87 page

VSC8540RT

DS60001603E-page 60

 2022 Microchip Technology Inc. and its subsidiaries

6.5.5

ENHANCED LED CONTROL

6.6

Clause 45 Registers to Support Energy-Efficient Ethernet and 802.3bf

This section describes the Clause 45 registers that are required to support energy-efficient Ethernet. Access to these

registers is through the IEEE standard registers 13 and 14 (MMD access control and MMD data or address registers).

The following table lists the addresses and register names in the Clause 45 register page space. When the link is down,

0 is the value returned for the x.180x addresses.

5:4

Clock squelch level

R/W

Select clock squelch level.

00: Automatically squelch clock to low when the link is not up,

is unstable, is up in a mode that does not support the genera-

tion of a recovered clock (10BASE-T), or is up in EEE mode

(100BASE-TX ).

01: Same as 00 except that the clock is also generated in

10BASE-T link-up mode. This mode also generates a recov-

ered clock output in EEE mode during reception of LP_IDLE.

10: Squelch only when the link is not up.

11: Disable clock squelch.

Note:

A clock from the Cu PHY will be output on the recov-

ered clock output in this mode when the link is

down.

When the CLK_SQUELCH_IN pin is set high, it squelches the

recovered clocks regardless of bit settings.

Reserved

Reserved.

2:0

Clock selection

R/W

000: Reserved.

001: Copper PHY recovered clock.

010–111: Reserved.

000

TABLE 6-53:

ENHANCED LED CONTROL, ADDRESS 25G (0X19)

Bit

Name

Access

Description

Default

15:8 LED pulsing duty

cycle control

R/W

Programmable control for LED pulsing duty cycle when

bit 30.12 is set to 1. Valid settings are between 0 and

198. A setting of 0 corresponds to a 0.5% duty cycle and

198 corresponds to a 99.5% duty cycle. Intermediate

values change the duty cycle in 0.5% increments.

0x00

7:0

Reserved

Reserved.

TABLE 6-54:

CLAUSE 45 REGISTERS PAGE SPACE

Address

Name

1.1

PMA/PMD status 1

1.1800

PMA/PMD time sync capable

1.1801

PMA/PMD delay Tx max.

1.1803

PMA/PMD delay Tx min.

1.1805

PMA/PMD delay Rx max.

1.1807

PMA/PMD delay Rx min.

3.1

PCS status 1

3.20

EEE capability

3.22

EEE wake error counter

TABLE 6-52:

RECOVERED CLOCK CONTROL, ADDRESS 23G (0X17) (CONTINUED)

Bit

Name

Access

Description

Default

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