PCA9541ADSLASH03 datasheet(7/45 Pages) NXP

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PCA9541A

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Product data sheet

Rev. 5 — 24 April 2014

7 of 45

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while logic 0 selects a write operation.

Remark: Reserved I2C-bus addresses must be used with caution since they can interfere

with:

• ‘reserved for future use’ I2C-bus addresses (1111 1XX)

• slave devices that use the 10-bit addressing scheme (1111 0XX)

7.2 Command Code

Following the successful acknowledgement of the slave address, the bus master sends a

byte to the PCA9541A, which is stored in the Command Code register.

The 2 LSBs are used as a pointer to determine which register is accessed.

If the auto-increment flag is set (AI = 1), the two least significant bits of the Command

Code are automatically incremented after a byte has been read or written. This allows the

user to program the registers sequentially or to read them sequentially.

• During a read operation, the contents of these bits will roll over to 00b after the last

allowed register is accessed (10b).

• During a write operation, the PCA9541A acknowledges bytes sent to the IE and

CONTROL registers, but does not acknowledge a byte sent to the Interrupt Status

over to 00b but stay at 10b.

Only the 2 least significant bits are affected by the AI flag.

Unused bits must be programmed with zeros. Any command code (write operation)

different from ‘000AI 0000’, ‘000AI 0001’, and ‘000AI 0010’ are not acknowledged. At

power-up, this register defaults to all zeros.

Each system master controls its own set of registers, however they can also read specific

bits from the other system master.

Fig 6.

Command Code

Table 4.

Command Code register

Type

R/W

interrupt enable

CONTROL

R/W

control switch

ISTAT

R only

interrupt status

not allowed

002aab391

auto-increment

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