PCA9541ADSLASH03 datasheet(21/45 Pages) NXP

21 / 45 page

PCA9541A

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Product data sheet

Rev. 5 — 24 April 2014

21 of 45

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

8.5 Bus transactions

Remark: If a third data byte is sent, it is not acknowledged by the PCA9541A.

Remark: If a fourth data byte is read, the first register is accessed.

Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit

002aab607

1 A3 A2 A1 A0 0

slave address

R/W

START condition

acknowledge

from slave

00010000

command code register

auto

increment

acknowledge

from slave

STOP

condition

acknowledge

from slave

acknowledge

from slave

data

Interrupt Enable (IE)

data control register

(CONTROL)

(1) xx = 00: Interrupt Enable register

xx = 01: Control register

xx = 10: INT register

(2) xx = 00: Control register

xx = 01: INT register

xx = 10: Interrupt Enable register

(3) xx = 00: INT register

xx = 01: Interrupt Enable register

xx = 10: Control register

Fig 14. Read the 3 registers using the Auto-Increment (AI) bit

002aab608

1 A3 A2 A1 A0 0

slave address

R/W

START condition

acknowledge

from slave

000100

command code register

access to register

xx = 00, 01, or 10

auto

increment

acknowledge

from slave

STOP

condition

no acknowledge

from master

acknowledge

from master

(1)

(2)

re-START

condition

1 A3 A2 A1 A0 1

slave address

R/W

acknowledge

from slave

acknowledge

from master

(3)

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