PCA9541ADSLASH03 datasheet(13/45 Pages) NXP

номер детали	PCA9541AD/03

подробное описание детали	2-to-1 I2C-bus master selector with interrupt logic and reset

PDF	45 Pages

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производитель	NXP [NXP Semiconductors]

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PCA9541A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 24 April 2014

13 of 45

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

Current status of the I2C-bus is determined by the bits MYBUS, NMYBUS, BUSON and

NBUSON is one of the following:

• The master reading its Control Register does not have control and the I2C-bus is off.

• The master reading its Control Register does not have control and the I2C-bus is on.

• The master reading its Control Register has control and the I2C-bus is off.

• The master reading its Control Register has control and the I2C-bus is on.

‘I2C-bus off’ means that upstream and downstream channels are not connected together.

‘I2C-bus on’ means that upstream and downstream channels are connected together.

Remark: Only the 4 LSBs of the Control Register are described in Table 12 since only

those bits control the I2C-bus control. The logic value for the 4 MSBs is specific to the

application and are not discussed in the table.

The read sequence is performed by the master as:

S - 111xxxx0 - 000x0001 - Sr - 111xxxx1 - DataRead - P

The write sequence is performed by the master as:

S - 111xxxx0 - 000x0001 - DataWritten - P

PCA9541AD/03 датащи(PDF) 13 Page - NXP Semiconductors