SMS64 datasheet(12/24 Pages) SUMMIT

12 / 24 page

SMS64

Preliminary

Summit Microelectronics, Inc

2060 2.22 10/09/03

The SMS64 can be configured to latch a forced

shutdown until either power is recycled to the device

or until all the VM inputs of the channels used in

sequencing have fallen below 0.8V. Note: With the

latter configuration and with the OFF sensors disabled,

the SMS64 will not latch a force shutdown command.

RST_A# OUTPUT

RST_A# has eight sources for activation (see

Figure 5). Any one of the voltage monitor UV/OV

outputs can be programmed as a source. If a selected

UV/OV condition occurs, the RST_A# output will be

driven low and remain low so long as the fault

condition is present. If the fault condition is cleared,

RST_A# will remain low for tPRTO (programmed reset

timeout period) and then return high.

If the MR# input is taken low, RST_A# will be

asserted. RST_A# will remain active so long as MR#

is low, and will continue driving the RST_A# output for

tPRTO after MR# returns high. The affect of the MR#

input on RSTA# cannot be bypassed or disabled.

If the Longdog timer is enabled, RST_A# will be

driven low and remain low for tPRTO after a Longdog

time out period.

During power-on sequencing RST_A# can be

cleared by a selected PUP output going active,

provided there are no other RST_A# triggers active

and that RST_A# has been triggered prior to this

event.. This allows RST_A# to be cleared prior to

RST_B#: thereby, providing a mechanism to bring one

portion of circuitry out of reset before another.

RST_B# OUTPUT

RST_B# has eight sources for activation (see

Figure 5). Any one of the voltage monitor UV/OV

outputs can be programmed as a source. If a selected

UV/OV condition occurs, the RST_B# output will be

driven low and remain low so long as the fault

condition is present. If the fault condition is cleared,

RST_B# will remain low for tPRTO and then return high.

If the MR# input is taken low, RST_B# will be

asserted. RST_B# will remain active so long as MR#

is low, and will continue driving the RST_B# output for

tPRTO after MR# returns high. The affect of the MR#

input on RSTB# cannot be bypassed or disabled.

If the Longdog timer is enabled, RST_B# will be

driven low and remain low for tPRTO after a Longdog

time out period.

IRQ# OUTPUT

The IRQ# circuitry is disabled during power-on

sequencing until all reset have cleared and the reset

interval (tPRTO) has timed out.

This allows the

application circuit to become fully operational before

an interrupt can occur. Interrupts are also disabled

during power-off sequencing and whenever the FS#

input is asserted.

IRQ# has seven sources of activation (see Figure

5). Any one of the voltage monitor UV/OV outputs can

be programmed as a source. If a selected UV/OV

condition occurs, the IRQ# output will be driven low

and remain low so long as the fault condition is

present.

The IRQ# output will be asserted if the Watchdog

timer times out. The Watchdog timer can be bypassed

by programming it off.

After the UV/OV condition has cleared or after the

Watchdog timer times out, the IRQ# output can be

cleared by two events. If either RST_A# or RST_B#

times out and returns high, the IRQ# output will be

cleared. The IRQ# output will also be cleared by a low

to high transition on the WLDI input. IRQ# can be

cleared under software control by writing 10[HEX] to the

command register.

HEALTHY# OUTPUT

The HEALTHY# output reflects the state of all of

the VM inputs (see Figure 5). The HEALTHY# output

will be driven low if there are no fault conditions

present.

APPLICATIONS INFORMATION (CONTINUED)

SMS64 датащи(PDF) 12 Page - Summit Microelectronics, Inc.

SMS64 датащи(HTML) 12 Page - Summit Microelectronics, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL