SMS64

Preliminary

Summit Microelectronics, Inc

2060 2.22 10/09/03

5

Pin

Number

Pin

Type

Pin Name

Pin Description

24

PWR

GND

GND is the ground for both the analog and digital portions of the internal

circuitry. It is internally tied to pin 15. (Both pins should be tied to system ground).

25

O

IRQ#

The interrupt output is an active low open-drain output. It will be driven low

whenever the Watchdog timer times out or whenever an enabled under-voltage or

over-voltage condition on a VM input exists.

The IRQ# signal is held in an inactive state during the power-on and

power-off sequence.

26

O

RST_B#

During the power-on sequence RST_B# will be asserted (driven low) until the

entire power-on sequence has been completed and the programmable reset

interval timer (tPRTO) has elapsed.

RST_B# will be forced low by asserting the MR# input. It will remain low so long

as the MR# input is low plus the programmed reset time out period for RST_B#.

RST_B#

will be asserted whenever an enabled UV/OV condition exists.

The RST_B# is an active low open drain output.

27

O

RST_A#

During the power-on sequence RST_A# will be driven low and will remain low

until a selected PUP output has become active. and the triggers for RST_A# are

inactive. In this manner the RST_A# can be used to release a portion of the circuitry

from reset before the entire system is energized.

RST_A# will be forced low by asserting the MR# input. It will remain low so long

as the MR# input is low plus the programmed reset time out period for RST_A#.

RST_A#

will be asserted whenever an enabled UV/OV condition exists.

The RST_A# is an active low open drain output.

28

O

HEALTHY#

The healthy output is used to signal that the VM inputs are not generating any

under-voltage or over-voltage conditions.

30

I

WLDI

WLDI is the Watchdog and Longdog timers’ interrupt input. A low to high

transition on the WLDI input will clear both the Watchdog and Longdog timers,

effectively starting a new time-out period.

If WLDI is stuck low and no low-to-high transition is received within the

(programmed Longdog time-out) RESET# will be driven low. Refer to Figure 5 for a

detailed illustration.

Holding WLDI high will block interrupts from occurring but will not block the

Longdog from timing out and generating a reset. Refer to Figure 3 for a detailed

illustration of the relationship between IRQ#, RESET#, and WLDI.

31

I

32

I

33

I

34

I

35

I

36

I

The VM pins are the voltage monitor inputs.

The input voltage is either

preset reference voltage of 0.5V.

PIN DESCRIPTIONS CONT’D