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SMS45 датащи(PDF) 13 Page - Summit Microelectronics, Inc.

номер детали SMS45
подробное описание детали  Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory
PDF  20 Pages
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производитель  SUMMIT [Summit Microelectronics, Inc.]
домашняя страница  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMS45 датащи(HTML) 13 Page - Summit Microelectronics, Inc.

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13
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 10. I2C Operating Characteristics
2047 Table10 4.0
Figure 9. I2C Operating Characteristics
I2C PROGRAMMING INFORMATION
Note (1): These values are guaranteed by design.
MEMORY OPERATION
Data for the configuration registers and the memory array
are read and written via an industry standard two-wire
interface. The bus was designed for two-way, two-line
serial communication between different integrated cir-
cuits. The two lines are a serial data line (SDA) and a
serial clock line (SCL). The SDA line must be connected
to a positive supply by a pull-up resistor, located some-
where on the bus. See Memory Operating Characteris-
tics: Table 10 and Figure 9.
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. In all cases the SMS45 will be a Slave device, since
it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as start or stop condition.
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
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