SMS45 datasheet(6/20 Pages) SUMMIT

6 / 20 page

SMS45

2079 1.2 05/24/04

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

PIN DESCRIPTIONS

V0, V1, V2, V3 (16, 2, 3, 14)

These inputs are used as the voltage monitor inputs and

as the voltage supply for the SMS45. Internally they are

diode ORed and the input with the highest voltage

potential will be the default supply voltage (VDD_CAP).

The RESET# output will be valid if any one of the four inputs

is above 1V. However, for full device operation at least one

of the inputs must be at 2.7V or higher.

The sensing threshold for each input is independently

programmable in 5mV increments from 0.6V to 1.875V or

15mV increments from 1.8V to 5.625V. Also, the occur-

rence of an under- or over-voltage condition that is detected

as a result of the threshold setting can be used to generate

a RESET#. The programmable nature of the threshold

voltage eliminates the need for external voltage divider

networks.

GND

Power supply return.

MR# (1)

The manual reset input always generates a RESET#

output whenever it is driven low. The duration of the

RESET# output pulse will be initiated when MR# goes low

and it will stay low for the duration of MR# low plus the

programmed reset time-out period (tPRTO). If MR# is

brought low during a power-on cascade of the PUP#s the

cascade will be halted for the reset duration, and will then

resume from the point at which it was interrupted. MR#

must be held low during a configuration register write. This

signal is pulled up internally through a 50k

Ω resistor.

RESET# (11)

The reset output is an active low open drain output. It will

be driven low whenever the MR# input is low or whenever

an enabled under-voltage or over-voltage condition exists.

The four voltage monitor inputs are always functioning, but

their ability to generate a reset is programmable (configu-

Figure 2. RESET# Timing with MR#

ration register 4). Refer to Figures 2 and 3 for a detailed

illustration of the relationship between MR#, RESET# and

the VIN levels.

VDD_CAP (12)

The VDD_CAP pin connects to the internal supply voltage

for the SMS45. A capacitor is placed on this pin to filter

supply noise as well as hold up the device in the event of

power failure. The voltage on this node is determined by the

highest input voltage.

Loading of this pin should be

minimized to prevent excessive power dissipation in the

part.

WLDI (15)

Watchdog timer input. A high-to-low transition on the WLDI

input will clear the watchdog timer, effectively starting a

new time-out period. This signal is pulled up internally

through a 50k

Ω resistor.

If WLDI is stuck low and no high-to-low transition is

received within the programmed tPWDTO period (pro-

grammed watchdog time-out) RESET# will be driven low.

Refer to Figure 4 for a detailed illustration.

Holding WLDI low will not block the watchdog from timing

out and generating a reset. Refer to Figure 4 for a detailed

illustration of the relationship between RESET# and WLDI.

tPRTO

2047 Fig04 3.0

RESET#

WLDI

tPRTO

tPWDTO

Figure 3. RESET# Timing

Figure 4. Watchdog and WLDI Timing

RESET#

tPRTO

V0 — V3

tDRST

VPTH-UV

MR#

RESET#

tDMRRST

tPRTO

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