10

SMS44

2047 2.3 10/23/00

SUMMIT MICROELECTRONICS, Inc.

They are programmed in register 7. See Figure 5.

Sequencing will always occur as indicated in the flow

chart.

MEMORY OPERATION

Data for the configuration registers and the memory array

are read and written via an industry standard two-wire

interface. The bus was designed for two-way, two-line

serial communication between different integrated cir-

cuits. The two lines are a serial data line (SDA) and a serial

clock line (SCL). The SDA line must be connected to a

positive supply by a pull-up resistor, located somewhere

on the bus.

See Memory Operating Characteristics:

Table 8 and Figure 8.

Figure 7. Sequence Flow Chart

Yes

No

Sequencing

Enabled

Turn On PUP#1

2047 Fig07 2.1

Yes

No

V1

Turn On PUP#2

Yes

No

V2

Turn On PUP#3