ADSP-SC591 datasheet(21/145 Pages) AD

21 / 145 page

Rev. A

Page 21 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

• Hardware reset—the SYS_HWRST input signal asserts

active (pulled down).

• Core only reset—affects only the core. The core is not

accessed by any bus requester when in reset state.

• Trigger request (peripheral).

Clock Generation Unit (CGU)

The ADSP-2159x/ADSP-SC59x processors support two inde-

pendent PLLs. Each PLL is part of a clock generation unit

(CGU). Each CGU can be either driven externally by the same

clock source or driven by separate sources, thus providing flexi-

bility in determining the internal clocking frequencies for each

clock domain.

Frequencies generated by each CGU are derived from a com-

mon multiplier with different divider values available for each

output.

The CGU generates all on-chip clocks and synchronization sig-

nals. Multiplication factors are programmed to define the

PLLCLK frequency.

Programmable values divide the PLLCLK frequency to generate

the core clock (CCLK), the system clocks, the DDR3/DDR3L

clock (DCLK), and the output clock (OCLK). For more infor-

mation on clocking, see the ADSP-2159x/ADSP-SC591/SC592/

SC594 SHARC+ Processor Hardware Reference.

Writing to the CGU control registers does not affect the behav-

ior of the PLL immediately. Registers are first programmed with

a new value and the PLL logic executes the changes to ensure

smooth transitions from the current conditions to the new

conditions.

System Crystal Oscillator

The processor can be clocked by an external crystal

(see Figure 6), a sine wave input, or a buffered, shaped clock

derived from an external clock oscillator. If using an external

clock, it must be compatible with the VIHCLKIN and VILCLKIN

specifications and must not be halted, changed, or operated

below the specified frequency during normal operation (see the

Operating Conditions section). This signal is connected to the

SYS_CLKINx pin of the processor. When using an external

clock, the SYS_XTALx pin must be left unconnected. Alterna-

tively, because the processor includes an on-chip oscillator

circuit, an external crystal can be used.

For fundamental frequency operation, use the circuit shown in

Figure 6. A parallel resonant, fundamental frequency, micro-

processor grade crystal is connected across the SYS_CLKINx

pin and the SYS_XTALx pin.

The two capacitors and the series resistor, shown in Figure 6,

fine tune phase and amplitude of the sine frequency. The capac-

itor and resistor values shown in Figure 6 are typical values

only. The capacitor values are dependent upon the load capaci-

tance recommendations of the crystal manufacturer and the

physical layout of the printed circuit board (PCB). The resistor

value depends on the drive level specified by the crystal

manufacturer. The user must verify the customized values based

on careful investigations on multiple devices over the required

temperature range.

Clock Distribution Unit (CDU)

The two clock generation units each provide outputs that feed a

clock distribution unit (CDU). The clock outputs

CLKO0–CLKO12 are connected to various targets. For more

information, refer to the ADSP-2159x/ADSP-SC591/SC592/

SC594 SHARC+ Processor Hardware Reference.

Clock Out/External Clock

The SYS_CLKOUT output pin has programmable options to

output divided down versions of the on-chip clocks. By default,

the SYS_CLKOUT pin drives a buffered version of the

SYS_ CLKIN0 input. Refer to the ADSP-2159x/ADSP-SC591/

SC592/SC594 SHARC+ Processor Hardware Reference to

change the default mapping of clocks.

Booting

The processors have several mechanisms for automatically load-

ing internal and external memory after a reset. The boot mode is

defined by the SYS_BMODE[n] input pins. There are two cate-

gories of boot modes. In flash boot modes, the processors

actively load data from serial memories. In external host boot

modes, the processors receive data over a serial interface from

an external host device.

The boot modes are shown in Table 7. These modes are imple-

mented by the SYS_BMODE[n] bits of the reset configuration

initiated resets.

In the ADSP-SC59x processors, the Arm Cortex-A5 (Core 0)

controls the boot process, including loading all internal and

external memory. Likewise, in the ADSP-2159x processors, the

SHARC+ (Core 1) controls the boot function. The option for

secure boot is available on all models.

Figure 6. External Crystal Connection

SYS_CLKIN

TO PLL

CIRCUITRY

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. VALID

FREQUENCY RANGE IS 20 MHz TO 30 MHz FOR SYS_CLKIN.

27pF*

SHARC® PROCESSOR

SYS_XTAL

27pF*

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