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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADSP-SC591 датащи(PDF) 39 Page - Analog Devices |
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ADSP-SC591 датащи(HTML) 39 Page - Analog Devices |
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39 / 145 page  Rev. A | Page 39 of 145 | April 2022 ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 Table 13. ADSP-SC59x Signal Multiplexing for Port C Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap PC_00 LP1_D1 TWI4_SCL1 TRACE0_D04 SPI1_SEL4 PC_01 LP1_D2 TWI4_SDA1 TRACE0_D05 SPI2_SEL42 PC_02 LP1_D3 TWI5_SCL1 TRACE0_D06 SPI1_SEL62 PC_03 LP1_D4 TWI5_SDA1 TRACE0_D07 SPI2_SEL62 PC_04 LP1_D5 OSPI0_SEL22 PC_05 LP1_D6 OSPI0_SEL32 TM0_TMR08 PC_06 LP1_D7 SPI1_RDY PC_07 LP1_CLK TM0_TMR09 SYS_FAULT PC_08 OSPI0_CLK1 PPI0_D16 PC_09 OSPI0_D31 PPI0_D17 PC_10 OSPI0_D21 PPI0_D18 PC_11 OSPI0_MOSI1 PPI0_D19 PC_12 OSPI0_MISO1 PPI0_D20 PC_13 OSPI0_D71 PPI0_D21 PC_14 OSPI0_D61 PPI0_D22 PC_15 OSPI0_D51 PPI0_D23 1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that their associated pins are as close as possible to each other 2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to other associated signals of the same peripheral. Table 14. ADSP-SC59x Signal Multiplexing for Port D Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap PD_00 OSPI0_D41 PD_01 OSPI0_SEL12 PPI0_D06 PD_02 UART1_RTS1 C2_FLG10 ETH0_CRS PD_03 UART1_CTS1 C1_FLG11 LP0_ACK ETH0_PTPAUXIN2 PD_04 UART1_RX1 OSPI0_DQS1 PPI0_D07 TM0_ACI01 PD_05 UART1_TX1 PPI0_D08 ETH0_PTPAUXIN1 PD_06 UART0_CTS1 ETH0_RXERR PD_07 UART0_RTS1 ETH0_COL PD_08 UART0_RX1 TM0_ACI00 PD_09 UART0_TX1 PD_10 UART2_RX1 PPI0_D09 TM0_ACI02 PD_11 UART2_TX1 PPI0_D10 PD_12 TM0_TMR06 UART2_RTS1 PPI0_D11 PD_13 TM0_TMR07 UART2_CTS1 PPI0_D12 PD_14 TWI4_SCL1 LP1_ACK C2_FLG09 PPI0_D13 PD_15 TWI4_SDA1 TM0_TMR15 PPI0_D14 1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that their associated pins are as close as possible to each other 2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to other associated signals of the same peripheral. |
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