ADSP-SC591 datasheet(96/145 Pages) AD

номер детали	ADSP-SC591

подробное описание детали	SHARC Dual-Core DSP with Arm Cortex-A5

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96 / 145 page

Rev. A

Page 96 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

SPI Port—SPIx_RDY Master Timing

SPIx_RDY is used to provide flow control. CPOL and CPHA are configuration bits in the SPIx_CTL register, whereas LEADX, LAGX,

and STOP are configuration bits in the SPIx_DLY register.

Table 59. SPI Port—SPIx_RDY Master Timing1

1 All specifications apply to all three SPIs.

Parameter

Conditions

Min

Max

Unit

Timing Requirement

tSRDYSCKM

Setup Time for SPIx_RDY

Deassertion Before Last Valid

Data SPIx_CLK Edge

(2 + 2 × BAUD2) × tCDU_CLKO6 +11

2 BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1.

Switching Characteristic

tDRDYSCKM

3 Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero.

Assertion of SPIx_RDY to First

SPIx_CLK Edge of Next Transfer

BAUD = 0, CPHA = 0 4.5 × tCDU_CLKO6

5.5 × tCDU_CLKO6 + 12

BAUD = 0, CPHA = 1 4 × tCDU_CLKO6

5 × tCDU_CLKO6 + 12

BAUD > 0, CPHA = 0 (1 + 1.5 × BAUD2) × tCDU_CLKO6

(2 + 2.5 × BAUD2) × tCDU_CLKO6 +12 ns

BAUD > 0, CPHA = 1 (1 + 1 × BAUD2) × tCDU_CLKO6

(2 + 2 × BAUD2) × tCDU_CLKO6 + 12 ns

Figure 26. SPIx_RDY Setup Before SPIx_CLK

SPIx_CLK

(CPOL = 0)

SPIx_CLK

(CPOL = 1)

tSRDYSCKM

SPIx_RDY

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