PT2000 datasheet(90/148 Pages) NXP

90 / 148 page

NXP Semiconductors

PT2000

8.3.2

Configuration register

8.3.2.1

Flash_enable register

This is a 6 bit configuration register which includes the following parameters:

• Checksum_disable. If set, this bit disables the effects of a failed checksum, so microcore execution is not stopped

• Pre_flash_enable. This bit “freezes” the CRAM so the micro-controller cannot further modify the configuration code unless a specific

unlock code is written into register unlock_reg. It enables the signature_unit (See Signature unit on page 72)

• Flash_enable. This bit enables the microcores. It can only be set by the signature_unit after a successful checksum calculation

• En_dual_microcore. This bit is used to enable the dual microcore mode. Note that when using dual microcore ck_per (refer to

Table 136, Clock_Prescaler (1A0h)) set to lower than three, there are some limitations regarding C/DRAM access.

• Checksum_irq_en. If this bit is '1', an interrupt on the_irq_device pin is done in case a CRAM corruption detected

• Checksum_failure. This bit sets to '1' when a mismatch is found between the calculated checksum and the checksum code stored in

the appropriate registers (refer to Table 66, checksum_h (108h, 128h, 148h) and Table 67, checksum_l (109h, 129h, 149h)). This bit

sets when a checksum calculation fails, even if the checksum is disabled. This bit resets each time the pre_flash_enable bit sets to '1'

to lock the memory.

8.3.2.2

Control register microcore0

• Control_register: these 8 bits can be used to control the execution of the micro-program of uc0, providing control bits which can be read

by the micro-program. For instance one bit could be used to enable/disable recharge pulses on the channel or to re-enable the actuation

after an error condition has been detected.

• Control_register_shared: according to a configuration bit stored in the “control_register_split” register (refer to Table 77,

Dac_rxtx_cr_config (112h, 132h, 152h)), these 8 bits can be used either as control (like the other 8 bits) or like status (like the status

register, refer to Table 63, status_reg_uc0 (105h, 125h, 145h)and Table 64, status_reg_uc1 (106h, 126h, 146h)). In this case, they can

only be read through the SPI, while they can be set by the “set control register bit” instruction.

Table 58. Flash_enable (100h, 120h, 140h)

Bit

Name

Reserved

checksum

_disable

flash_en

able

pre

flash_en

able

en_dual_

Reserved

chksum_irq

_en

chksum_f

ailure

R/W

r/w

Lock

yes, by

pre flash

enable

yes, by

itself

yes, by

pre flash

enable

yes

Reset

000000000

Table 59. Ctrl_reg_uc0 (101h, 121h, 141h)

Bit

Name

Control_register_Shared

Control_register

R/W

configurable r or r/w

r/w

Lock

Reset

00000000

PT2000 датащи(PDF) 90 Page - NXP Semiconductors

PT2000 датащи(HTML) 90 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL