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SP9841 датащи(PDF) 20 Page - Sipex Corporation

номер детали SP9841
подробное описание детали  8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC
PDF  32 Pages
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производитель  SIPEX [Sipex Corporation]
домашняя страница  http://www.sipex.com
Logo SIPEX - Sipex Corporation

SP9841 датащи(HTML) 20 Page - Sipex Corporation

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Figure 4. Timing.
CHARACTERISTICS
(Typical @ 25
°C with V
DD = +5V unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
Input Clock Pulse Width (t
CH, tCL)50
ns
Data Setup Time (t
DS)30
ns
Data Hold Time (t
DH)20
ns
CLK to SDO Propagation Delay (t
PD)
100
ns
DAC Register Load Pulse Width (t
LD)50
ns
Preset Pulse Width (t
PR)50
ns
Clock Edge to Load Time (t
CKLD)30
ns
Load Edge to Next Clock Edge(t
LDCK)60
ns
1
0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
FS
0
SDI
CLOCK
LOAD
VOUT
1
0
1
0
1
0
(FFH)
(08H)
SERIAL
DATA IN
SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; VIN(X) = 1.5V; VREFL = 0V)
1
0
SERIAL
DATA OUT
CLOCK
LOAD
VOUT
tDS
tCH
tCL
tLD
tS
tLDCK
±1 LSB
ERROR BAND
tCLKD
tPD
tDH
AX or DX
1
0
PRESET
tS
tPR
±1 LSB
ERROR BAND
(FFH)
(08H)
VOUT
Table 2. Logic Control Input Truth Table.
SDI
CLK
LOADH
PRESETL
LOGIC OPERATION
X
L
L
H
No Change
Data
L
H
Shift In One Bit from SDI
Shift Out 12–clock delayed data at SDO
X
X
X
L
All DAC Registers Preset to 80
H (Note 1)
X
L
H
H
Load Serial Register Data into DAC(X) Register
Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high.



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