SP9841 datasheet(17/32 Pages) SIPEX

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tiple DAC applications without additional external

decoding logic.

The SP9841/9842 consume only 65 mW from a

single +5V power supply. The SP9841 is available in

24-pin plastic DIP and SOIC packages. The SP9842

is available in a space–saving 20–pin SOIC package.

For applications requiring code–controlled output

polarityreversalregardlessofthereferenceinputlevel

(i.e. four–quadrant multiplication), please see the

SP9840/SP9843 product data sheet.

USING THE SP9841/9842

Theory of Operation

EachoftheeightchannelsoftheSP9841/SP9842can

be used for signal reconstruction, as a programmable

dc source, or as a programmable gain/attenuation

block, multiplying an ac reference input by factors of

0 to 1.992. The rugged, wideband output amplifiers

provide both current sink and source capability for dc

applications, eventhosedrivingdifficultloads.Thedc

source mode mimics the functionality of a program-

mable trimpot with the added benefit of a low imped-

ance buffered output. The amplifier's bandwidth and

high open–loop gain allow its use in programmable

gain applications where even a low distortion, high

resolutionsignal (such asaudio) must begatedonand

off or gain–controlled over a –42 to +6dB range.

Each channel consists of a voltage–output DAC,

implemented using CMOS switches and thin–film

resistors in a inverted R–2R ladder configuration.

Each DAC drives the positive terminal of an op amp

–

DAC 1

DAC

OUT

OUT = 2 X VDAC when VREFL = 0V

= 2(D/256) X V

= D/128 X V

REFL

OUT = D/128 X (VIN – VREFL) +VREFL

Figure 1. DAC and Output Amplifier Circuit

configured for a non–inverting gain of 2 using equal

value thin–film feedback and gain–setting resistors.

Signal ground is the V

REFL pin, the common reference

input return for the 8 DAC–op amp channels. As

showninFigure1,theDACsectioncanbethoughtof

as a potentiometer across V

IN(X) to VREFL. When this

potentiometer reaches its maximum output value of

255/256timesV

IN, the output will be 1+(RFB/RGAIN) or

2 times the value of V

DAC (actually up to 1.9921875

times the input voltage, with V

REFL tied to ground).

When the potentiometer is at its minimum value of 0/

256,theoutputwilltrytobe0V,againassumingV

REFL

is tied to ground.

The true relation between the dc levels at the V

IN pin,

REFL and the output can be described as:

OUT = ((1 + RFB/RG) * (Data/256) * (VIN – VREFL)) + VREFL

where Data is programmable from 0 to 255, and R

FB = RG.

2.5

1.5

0.5

1.5

VREFL= 0V

VIN(X) (Volts)

D = FFH

D = 80H

D = 00H

1.0

0.5

1.0

2.0

3.0

2.5

1.5

0.75

2.25

VREFL= 1.5V

VIN(X) (Volts)

D =

80 H

D = 00H

1.5

0.5

1.0

2.0

3.0

Figure 2. a) Single–Quadrant, and b) Two–Quadrant Operation

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