© VITESSE SEMICONDUCTOR CORPORATION

Page 23

6/14/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7217

Multi-Gigabit Interconnect Chip

G52325-0, Rev. 3.0

Figure 19: RCLKn and RCLKNn Timing Waveforms with DUAL = 1

Table 14: General Receive AC Characteristics

NOTE: (1) The probability of correct data acquisition and recovery is 99% per FC-PH 4.3 Section 5.3.

Parameters

Description

Min.

Max.

Units

Conditions

Delay Between Rising Edge

of

RCLKn to Rising Edge

of

RCLKNn

-500

+500

ps

incoming data on Rx.

RCLKn to RCLKNn Skew

-500

500

ps

Deviation of

RCLKn rising

edge to

RCLKNn rising

edge. Nominal delay is 10 bit

times.

Period of

RCLKn and

RCLKNn

0.99 x

1.01 x

ps

Whether or not locked to

serial data, independent of

DUAL input.

Deviation of

RCLK/RCLKN Period

from

REFCLK Period

-1.0

1.0

%

Whether or not locked to

serial data, independent of

DUAL input.

Output Rise and Fall Time

—

2.4

ns

Latency from

RX0 to

REFCLK or RCLK

70.5bc-1.6ns

48.5bc-1.6ns

81.5bc+4.1ns

102.5bc+4.1ns

bc+ns

ENDEC=1, Recenter only

ENDEC=X, Recenter + Drift

Data Acquisition Lock Time

—

100

bc

Using K28.5+/K28.5- pattern.

tested on a sample basis.

Receive Data Total

Jitter Tolerance (p-p)

600

ps

IEEE 802.3z Clause 38.68,

tested on a sample basis.

Receive Data

Deterministic

Jitter Tolerance (p-p)

370

ps

IEEE 802.3z Clause 38.69,

tested on a sample basis.

RCLKNn

RCLKn

Delay

10

------------

±

=

±

=