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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VSC7217UC датащи(PDF) 22 Page - Vitesse Semiconductor Corporation |
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VSC7217UC датащи(HTML) 22 Page - Vitesse Semiconductor Corporation |
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22 / 36 page  VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7217 Mutli-Gigabit Interconnect Chip Page 22 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 6/14/00 G52325-0, Rev. 3.0 Figure 17: Receive Output Timing Waveforms with RMODE = 00 or 01 Table 12: Receive Output AC Characteristics with RMODE = 00 or 01 Figure 18: Receive Output Timing Waveforms with RMODE = 10 or 11 Table 13: Receive Output AC Characteristics with RMODE = 10 or 11 Parameters Description Min Max Units Conditions TCQ REFCLK Rising Edge to TTL Output Transition 2.58 ns - 0 bc 5.43 ns - 0 bc ns RMODE = 00 bc = Bit Clock TCQ REFCLK Rising Edge to TTL Output Transition 2.58 ns - 2 bc 5.43 ns - 2 bc ns RMODE = 01 bc = Bit Clock TQC TTL Output Transition to REFCLK Rising Edge TPER - TCQ_max ns Parameters Description Min Max Units Conditions TCQ RCLKn/RCLKNn Rising Edge to TTL Output Transition -1.25 ns + 4 bc 1.25 ns + 4 bc ns RMODE = 10 or 11 bc = Bit Clock TCQ TTL Output Transition to RCLKn/ RCLKNn Rising Edge TPER - TCQ_max TPER - TCQ_min ns DC RCLKn/RCLKNn Duty Cycle 50% - 1 ns 50% + 1 ns ns Measured at 1.4. V REFCLK (DUAL = 0) Rn(7:0) TBERRn KCHn IDLEn ERRn PSDETn RSDETn Valid Valid Valid TCQ_max TCQ_min REFCLK (DUAL = 1) TQC_min TPER RCLKn (DUAL = 0) Rn(7:0) TBERRn KCHn IDLEn ERRn PSDETn RSDETn Valid Valid Valid TCQ_max TCQ_min RCLKn/RCLKNn (DUAL = 1) TQC_min TPER |
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