AD8065 datasheet(30/68 Pages) AD

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Data Sheet

AD3552R

THEORY OF OPERATION

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Rev. A | 30 of 68

CRC Error Detection

The AD3552R features an optional CRC to provide error detection

for SPI transactions between the digital host (master) and the

AD3552R (slave).

CRC error detection allows SPI masters and slaves to detect

bit transfer errors with significant reliability. The CRC algorithm

involves using a seed value and polynomial division to generate

a CRC code. The master and slave both calculate the CRC code

independently and compare it to determine the validity of the

transferred data.

The AD3552R uses the CRC-8 standard with the following polyno-

mial:

x8+x2+x+1(Equation1)

CRC error detection is enabled with the CRC_EN and CRC_EN_B

bits in the INTERFACE_CONFIG_C register. The value of CRC_EN

is only updated if CRC_EN_B is set to the CRC_EN inverted value

in the same register write instruction. Therefore, to enable the CRC,

CRC_EN must be set to 0b01 while CRC_EN_B is set to 0b10 in

the same write transaction.

To disable the CRC, CRC_ENABLE must be set to 0b00 while

CRC_ENABLE_B is set to 0b11 in the same write transaction.

Writing inverted values to two separate fields reduces the chances

of CRC being enabled by mistake. CS must be brought high at the

end of the enable or disable write. The transaction following the

enabling of the CRC must already include the CRC byte, regardless

if it is a write or read operation. A register write transaction that

disables CRC must still include the CRC code at the end, but the

transaction following the disabling of the CRC does not have to

include the CRC byte.

Figure 76 and Figure 77 show how a CRC code is appended at the

end of a write or read transaction, respectively, in single SPI mode

(classic mode). For register writes, the digital host must generate

the CRC by performing the calculation described in Equation 1 on

the seed, the address, and the data. The AD3552R performs the

same calculation and shifts out the CRC code on SDO at the same

time as the host. The transaction is free of error if both CRC codes

match. For register reads, the host calculates the CRC on the seed,

the address, and a zero padding while the AD3552R calculates the

CRC on the seed, the address, and the readout data. Both nodes

then shift out the CRC code at the same time so that it can be

checked on both sides.

Figure 76. Basic SPI Write Frame with CRC

Figure 77. Basic SPI Read Frame with CRC

When accessing multibyte registers with CRC error detection ena-

bled, the CRC code is placed after all of the bytes of register data.

When CRC error detection is enabled, the AD3552R does not up-

date its register contents in response to a register write transaction

unless it receives a valid CRC code at the end of the register data.

If the CRC code is invalid, or if the digital host fails to transmit the

CRC code, the AD3552R does not update its register contents, and

the INVALID_OR_NO_CRC flag in the INTERFACE_STATUS_A

is written to this bit, and the correct CRC is required for the write to

clear the bit to take effect.

Table 11 shows the seed value used in the CRC code calculation

and how it is calculated for both single instruction mode and

streaming mode.

Table 11. CRC Seed Values and Extent of CRC Calculation

SPI Transaction Type

Single Instruction Mode

Streaming Mode, First Data Phase

Streaming Mode, Subsequent Data Phases

Read

SDI

0xA5, instruction phase, padding

No CRC sent

SDO

0xA5, instruction phase, read data

Least significant byte of address, read data

Write

SDI

0xA5, instruction phase, write data

Least significant byte of address, write data

SDO

0xA5, instruction phase, write data

Least significant byte of address, write data

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