AD8065 datasheet(49/68 Pages) AD

49 / 68 page

Data Sheet

AD3552R

REGISTERS

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Rev. A | 49 of 68

Table 31. Bit Descriptions for INTERFACE_CONFIG_C

Bits

Bit Name

Settings

Description

Reset

Access

each of its individual bytes for the register to be updated. Failure

to write data to the entire multibyte register (entity) results in

the register contents not being updated in memory, and the

PARTIAL_REGISTER_ACCESS flag in the INTERFACE_STATUS_A

1 Strict access mode. Multibyte registers require all bytes to be read/

written in full to avoid the PARTIAL_REGISTER_ACCESS bit being

flagged.

[4:2]

RESERVED

Reserved.

0x0

[1:0]

CRC_ENABLE_B

Inverted CRC Enable. This field must be written with the

complementary value of the CRC_ENABLE field.

0x3

R/W

11 CRC disabled.

10 CRC enabled.

Interface Status A Register

Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A

This register flags several error conditions related to SPI communication and register addressing.

Table 32. Bit Descriptions for INTERFACE_STATUS_A

Bits

Bit Name

Settings

Description

Reset

Access

INTERFACE_NOT_READY

Interface Not Ready Error Flag. Indicates if the device

interface was not ready for a transaction when an SPI

read or write transaction was requested by the digital host

(master). This flag bit is set if an SPI frame begins before

the device is ready after a power-on reset. This error flag

is write‑1‑to‑clear (when this error flag is set, it can only

be reset by writing a 1 to this bit).

0x0

R/W1C

0 Interface not ready error not detected.

1 Interface not ready error detected.

RESERVED

Reserved.

0x0

CLOCK_COUNTING_ERROR

Clock Count Error Flag. Indicates if the incorrect number

of serial clock edges was detected in an SPI read or write

transaction (for example, if the transaction was terminated

in the middle of a byte). This error flag is write‑1‑to‑clear

0x0

R/W1C

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