AD8065 datasheet(62/68 Pages) AD

62 / 68 page

Data Sheet

AD3552R

REGISTERS

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Rev. A | 62 of 68

Table 52. Bit Descriptions for HW_LDAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

0 Data is latched in DAC Register 0 when the LDAC pin is asserted.

1 LDAC signal masked for Channel 0. DAC register is not updated when

LDAC is asserted.

DAC Register for Channel 0, Precision Mode

Address: 0x38, Reset: 0x000000, Name: CH0_DAC_24B

This register contains the data currently played on DAC Channel 0.

Table 53. Bit Descriptions for CH0_DAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

DAC_DATA0

Channel 0 DAC Data.

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

DAC Register for Channel 1, Precision Mode

Address: 0x3B, Reset: 0x000000, Name: CH1_DAC_24B

This register contains the data currently played on DAC Channel 1.

Table 54. Bit Descriptions for CH1_DAC_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

DAC_DATA1

Channel 1 DAC Data.

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

DAC Page Register, Precision Mode

Address: 0x3E, Reset: 0x000000, Name: DAC_PAGE_24B

This register is used to write data to one or both channels according to the configuration of the SEL_CHx bits in the CH_SELECT_24B register.

It can be used to write both channels simultaneously without using the LDAC signal.

Table 55. Bit Descriptions for DAC_PAGE_24B

Bits

Bit Name

Settings

Description

Reset

Access

[23:8]

DAC_PAGE

DAC Page Data. Following a write to this register, the DAC code loaded into this register is

copied into the DAC register of any channels selected in the CH_SELECT_24B register.

0x0

R/W

[7:0]

RESERVED

Reserved.

0x0

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