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INA849 датащи(PDF) 21 Page - Texas Instruments |
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INA849 датащи(HTML) 21 Page - Texas Instruments |
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21 / 28 page ![]() 11.2 Layout Example GND GND IN– RG RG 4 IN+ 1 2 3 G02+ OUT+ OUT– 9 G02– 12 11 10 PAD R2 GND VIN+ VIN– R1 GND RG VS– C2 VS+ C1 C4 C3 VCLAMP– VCLAMP+ VOCM INN INP Use ground pours for shielding the input signal pairs Place bypass capacitors as close to IC as possible RG VIN– VIN+ VS+ VS– R2 R1 C2 C1 RG INA851 RG R3 R4 C7 ADC C3 C4 Short OUTx to G02x for output stage G = 0.2 Connect feedback capacitors between OUTx and FDA_INx (optional) INP INN C7 R3 R4 OUT– OUT+ VOCM Consider utilizing thermal vias for heatsinking Cutouts on ground planes underneath input pins (1, 4, 6, 15) can reduce stray capacitance, for better phase margin C5 C6 C6 C5 GND GND Figure 11-1. Example Schematic and Associated PCB Layout www.ti.com INA851 SBOS999 – MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: INA851 |
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